Low level access to RISC-V processors

Vadim Kaushan c3ff23989e Bump version (0.5.2) 6 лет назад
.github 59d46795b2 A unified contributing experience. 6 лет назад
bin 7112ef8af2 Regenerate blobs 6 лет назад
ci 698cb306ea Enable gcc caching 6 лет назад
src ca797a35d8 Fix Misa::has_extension() 6 лет назад
.gitignore a51143d366 Implement asm functions 6 лет назад
.travis.yml 7d4919a67c Add MSRV policy 6 лет назад
CODE_OF_CONDUCT.md c1a3fe2dd9 Rename RISCV to RISC-V 6 лет назад
Cargo.toml c3ff23989e Bump version (0.5.2) 6 лет назад
README.md c1a3fe2dd9 Rename RISCV to RISC-V 6 лет назад
asm.S 5baba0cb32 Add write function for sstatus register 6 лет назад
asm.h a51143d366 Implement asm functions 6 лет назад
asm32.S a51143d366 Implement asm functions 6 лет назад
assemble.sh 427c3b9035 Generate binaries for 64-bit targets 6 лет назад
build.rs a51143d366 Implement asm functions 6 лет назад
check-blobs.sh a51143d366 Implement asm functions 6 лет назад

README.md

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riscv

Low level access to RISC-V processors

This project is developed and maintained by the RISC-V team.

Documentation

License

Copyright 2019 RISC-V team

Permission to use, copy, modify, and/or distribute this software for any purpose with or without fee is hereby granted, provided that the above copyright notice and this permission notice appear in all copies.

THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.

Code of Conduct

Contribution to this crate is organized under the terms of the Rust Code of Conduct, the maintainer of this crate, the RISC-V team, promises to intervene to uphold that code of conduct.