Low level access to RISC-V processors

Vadim Kaushan e2ed39decd Leave just team e-mail in authors 6 years ago
.github 59d46795b2 A unified contributing experience. 6 years ago
bin a51143d366 Implement asm functions 6 years ago
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src 16fdb16730 Update docs 6 years ago
.gitignore a51143d366 Implement asm functions 6 years ago
.travis.yml 7e2103e566 Check build on stable 6 years ago
CODE_OF_CONDUCT.md 59d46795b2 A unified contributing experience. 6 years ago
Cargo.toml e2ed39decd Leave just team e-mail in authors 6 years ago
README.md b03aae8850 Update README. 6 years ago
asm.S a51143d366 Implement asm functions 6 years ago
asm.h a51143d366 Implement asm functions 6 years ago
asm32.S a51143d366 Implement asm functions 6 years ago
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check-blobs.sh a51143d366 Implement asm functions 6 years ago

README.md

crates.io crates.io Build Status

riscv

Low level access to RISCV processors

This project is developed and maintained by the RISCV team.

Documentation

License

Copyright 2018 RISCV team

Permission to use, copy, modify, and/or distribute this software for any purpose with or without fee is hereby granted, provided that the above copyright notice and this permission notice appear in all copies.

THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.

Code of Conduct

Contribution to this crate is organized under the terms of the Rust Code of Conduct, the maintainer of this crate, the RISCV team, promises to intervene to uphold that code of conduct.