Low level access to RISC-V processors

LoGin 4241a97627 feat: Add update_sum method to Sstatus struct (#8) il y a 7 mois
.github afddf094a0 Merge branch 'master' of github.com:rust-embedded/riscv into riscv-rt-asm il y a 9 mois
riscv 4241a97627 feat: Add update_sum method to Sstatus struct (#8) il y a 7 mois
riscv-pac cadabef94f Minor releases il y a 9 mois
riscv-peripheral d51c622ca8 Cargo metadata for riscv-peripheral il y a 9 mois
riscv-rt 6cab675051 Patch merge origin 240405 (#5) il y a 8 mois
riscv-semihosting 3384fc8b19 Prepare for releases il y a 10 mois
.gitignore 4344b03e88 Remove bit_field dependency il y a 1 an
CODE_OF_CONDUCT.md 4bd6d68552 Update link (riscv to risc-v) il y a 4 ans
Cargo.toml b2183c696b Merge branch 'master' into add-peripheral il y a 10 mois
README.md b2183c696b Merge branch 'master' into add-peripheral il y a 10 mois

README.md

RISC-V crates

This repository contains various crates useful for writing Rust programs on RISC-V microcontrollers:

This project is developed and maintained by the RISC-V team.

Contribution

Unless you explicitly state otherwise, any contribution intentionally submitted for inclusion in the work by you, as defined in the Apache-2.0 license, shall be dual licensed as above, without any additional terms or conditions.

Code of Conduct

Contribution to this crate is organized under the terms of the Rust Code of Conduct, the maintainer of this crate, the RISC-V team, promises to intervene to uphold that code of conduct.