feat: update rust edition to 2024 and change `asm!` to `naked_asm!`

Cargo.lock

@@ -2,11 +2,20 @@
 # It is not intended for manual editing.
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@@ -58,6 +67,39 @@ dependencies = [
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@@ -138,9 +346,9 @@ dependencies = [
 
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@@ -359,9 +658,21 @@ dependencies = [
 
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+
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 ]
 
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+]
+
 [[package]]
 name = "rcore-console"
 version = "0.0.0"
@@ -428,6 +780,7 @@ dependencies = [
  "critical-section",
  "embedded-hal 1.0.0",
  "paste",
+ "riscv-macros",
  "riscv-pac",
 ]
 
@@ -437,6 +790,17 @@ version = "0.2.2"
 source = "registry+https://github.com/rust-lang/crates.io-index"
 checksum = "cf8b4cfb0da0528321d22daee4299a23a8c5ac8848623d716e898d2a9eec0694"
 
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+dependencies = [
+ "proc-macro2",
+ "quote",
+ "syn",
+]
+
 [[package]]
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@@ -508,10 +872,7 @@ dependencies = [
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- "naked-function",
- "rcore-console",
- "sbi-rt 0.0.3 (registry+https://github.com/rust-lang/crates.io-index)",
- "uart16550",
+ "axstd",
 ]
 
 [[package]]
@@ -522,11 +883,17 @@ dependencies = [
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  "rcore-console",
  "riscv 0.11.1",
- "sbi-testing 0.0.3-alpha.2 (registry+https://github.com/rust-lang/crates.io-index)",
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+
 [[package]]
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 version = "0.0.3"
@@ -544,6 +911,14 @@ dependencies = [
  "sbi-spec 0.0.8 (git+https://github.com/rustsbi/rustsbi?rev=4821073)",
 ]
 
+[[package]]
+name = "sbi-rt"
+version = "0.0.3"
+source = "git+https://github.com/rustsbi/rustsbi#99f4177fbed12c96c2c62121d51953b1bfa0ff43"
+dependencies = [
+ "sbi-spec 0.0.8 (git+https://github.com/rustsbi/rustsbi)",
+]
+
 [[package]]
 name = "sbi-spec"
 version = "0.0.7"
@@ -561,19 +936,15 @@ name = "sbi-spec"
 version = "0.0.8"
 source = "git+https://github.com/rustsbi/rustsbi?rev=4821073#4821073b56a7223781c11a49aba743785d89d3ea"
 dependencies = [
- "bitflags",
+ "bitflags 2.8.0",
 ]
 
 [[package]]
-name = "sbi-testing"
-version = "0.0.3-alpha.2"
-source = "registry+https://github.com/rust-lang/crates.io-index"
-checksum = "135c0f1ce07ede77a7e1c3daff35d20d37b54fd1037ac02ab9595c231518531e"
+name = "sbi-spec"
+version = "0.0.8"
+source = "git+https://github.com/rustsbi/rustsbi#99f4177fbed12c96c2c62121d51953b1bfa0ff43"
 dependencies = [
- "log",
- "riscv 0.11.1",
- "sbi-rt 0.0.3 (registry+https://github.com/rust-lang/crates.io-index)",
- "sbi-spec 0.0.7",
+ "bitflags 2.8.0",
 ]
 
 [[package]]
@@ -587,6 +958,17 @@ dependencies = [
  "sbi-spec 0.0.8 (git+https://github.com/rustsbi/rustsbi?rev=4821073)",
 ]
 
+[[package]]
+name = "sbi-testing"
+version = "0.0.3-alpha.2"
+source = "git+https://github.com/rustsbi/rustsbi#99f4177fbed12c96c2c62121d51953b1bfa0ff43"
+dependencies = [
+ "log",
+ "riscv 0.12.1",
+ "sbi-rt 0.0.3 (git+https://github.com/rustsbi/rustsbi)",
+ "sbi-spec 0.0.8 (git+https://github.com/rustsbi/rustsbi)",
+]
+
 [[package]]
 name = "scopeguard"
 version = "1.2.0"
@@ -642,6 +1024,12 @@ version = "1.2.0"
 source = "registry+https://github.com/rust-lang/crates.io-index"
 checksum = "a8f112729512f8e442d81f95a8a7ddf2b7c6b8a1a6f509a95864142b30cab2d3"
 
+[[package]]
+name = "static_assertions"
+version = "1.1.0"
+source = "registry+https://github.com/rust-lang/crates.io-index"
+checksum = "a2eb9349b6444b326872e140eb1cf5e7c522154d69e7a0ffb0fb81c06b37543f"
+
 [[package]]
 name = "strsim"
 version = "0.11.1"
@@ -650,15 +1038,44 @@ checksum = "7da8b5736845d9f2fcb837ea5d9e2628564b3b043a70948a3f0b778838c5fb4f"
 
 [[package]]
 name = "syn"
-version = "2.0.96"
+version = "2.0.98"
 source = "registry+https://github.com/rust-lang/crates.io-index"
-checksum = "d5d0adab1ae378d7f53bdebc67a39f1f151407ef230f0ce2883572f5d8985c80"
+checksum = "36147f1a48ae0ec2b5b3bc5b537d267457555a10dc06f3dbc8cb11ba3006d3b1"
 dependencies = [
  "proc-macro2",
  "quote",
  "unicode-ident",
 ]
 
+[[package]]
+name = "tock-registers"
+version = "0.8.1"
+source = "registry+https://github.com/rust-lang/crates.io-index"
+checksum = "696941a0aee7e276a165a978b37918fd5d22c55c3d6bda197813070ca9c0f21c"
+
+[[package]]
+name = "tock-registers"
+version = "0.9.0"
+source = "registry+https://github.com/rust-lang/crates.io-index"
+checksum = "2b9e2fdb3a1e862c0661768b7ed25390811df1947a8acbfbefe09b47078d93c4"
+
+[[package]]
+name = "toml_datetime"
+version = "0.6.8"
+source = "registry+https://github.com/rust-lang/crates.io-index"
+checksum = "0dd7358ecb8fc2f8d014bf86f6f638ce72ba252a2c3a2572f2a795f1d23efb41"
+
+[[package]]
+name = "toml_edit"
+version = "0.22.23"
+source = "registry+https://github.com/rust-lang/crates.io-index"
+checksum = "02a8b472d1a3d7c18e2d61a489aee3453fd9031c33e4f55bd533f4a7adca1bee"
+dependencies = [
+ "indexmap",
+ "toml_datetime",
+ "winnow",
+]
+
 [[package]]
 name = "uart16550"
 version = "0.0.1"
@@ -670,15 +1087,15 @@ name = "uart_xilinx"
 version = "0.2.0"
 source = "git+https://github.com/duskmoon314/uart-rs/#12be91421ad140f2a4bf4179578fd7a8fbc7ff5c"
 dependencies = [
- "bitflags",
+ "bitflags 2.8.0",
  "volatile-register",
 ]
 
 [[package]]
 name = "unicode-ident"
-version = "1.0.14"
+version = "1.0.16"
 source = "registry+https://github.com/rust-lang/crates.io-index"
-checksum = "adb9e6ca4f869e1180728b7950e35922a7fc6397f7b641499e8f3ef06e50dc83"
+checksum = "a210d160f08b701c8721ba1c726c11662f877ea6b7094007e1ca9a1041945034"
 
 [[package]]
 name = "utf8parse"
@@ -698,6 +1115,12 @@ version = "1.0.2"
 source = "registry+https://github.com/rust-lang/crates.io-index"
 checksum = "6a02e4885ed3bc0f2de90ea6dd45ebcbb66dacffe03547fadbb0eeae2770887d"
 
+[[package]]
+name = "volatile"
+version = "0.4.6"
+source = "registry+https://github.com/rust-lang/crates.io-index"
+checksum = "442887c63f2c839b346c192d047a7c87e73d0689c9157b00b53dcc27dd5ea793"
+
 [[package]]
 name = "volatile-register"
 version = "0.2.2"
@@ -780,6 +1203,63 @@ version = "0.52.6"
 source = "registry+https://github.com/rust-lang/crates.io-index"
 checksum = "589f6da84c646204747d1270a2a5661ea66ed1cced2631d546fdfb155959f9ec"
 
+[[package]]
+name = "winnow"
+version = "0.7.1"
+source = "registry+https://github.com/rust-lang/crates.io-index"
+checksum = "86e376c75f4f43f44db463cf729e0d3acbf954d13e22c51e26e4c264b4ab545f"
+dependencies = [
+ "memchr",
+]
+
+[[package]]
+name = "x2apic"
+version = "0.4.3"
+source = "registry+https://github.com/rust-lang/crates.io-index"
+checksum = "cbcd582541cbb8ef1dfc24a3c849a64ff074b1b512af723ad90056558d424602"
+dependencies = [
+ "bit",
+ "bitflags 1.3.2",
+ "paste",
+ "raw-cpuid 10.7.0",
+ "x86_64 0.14.13",
+]
+
+[[package]]
+name = "x86"
+version = "0.52.0"
+source = "registry+https://github.com/rust-lang/crates.io-index"
+checksum = "2781db97787217ad2a2845c396a5efe286f87467a5810836db6d74926e94a385"
+dependencies = [
+ "bit_field",
+ "bitflags 1.3.2",
+ "raw-cpuid 10.7.0",
+]
+
+[[package]]
+name = "x86_64"
+version = "0.14.13"
+source = "registry+https://github.com/rust-lang/crates.io-index"
+checksum = "c101112411baafbb4bf8d33e4c4a80ab5b02d74d2612331c61e8192fc9710491"
+dependencies = [
+ "bit_field",
+ "bitflags 2.8.0",
+ "rustversion",
+ "volatile",
+]
+
+[[package]]
+name = "x86_64"
+version = "0.15.2"
+source = "registry+https://github.com/rust-lang/crates.io-index"
+checksum = "0f042214de98141e9c8706e8192b73f56494087cc55ebec28ce10f26c5c364ae"
+dependencies = [
+ "bit_field",
+ "bitflags 2.8.0",
+ "rustversion",
+ "volatile",
+]
+
 [[package]]
 name = "xtask"
 version = "0.1.0"
@@ -795,7 +1275,7 @@ version = "0.0.0"
 source = "git+https://github.com/rustsbi/xuantie#7a521c0400dc7edb7a3ee103206dd8246c78d542"
 dependencies = [
  "bit_field",
- "bitflags",
+ "bitflags 2.8.0",
  "plic",
  "volatile-register",
 ]

Cargo.toml

@@ -1,9 +1,9 @@
 [workspace]
-resolver = "2"
+resolver = "3"
 members = ["prototyper", "bench-kernel", "test-kernel", "supervisor", "xtask"]
 
 [workspace.package]
-edition = "2021"
+edition = "2024"
 license = "MulanPSL-2.0 OR MIT"
 repository = "https://github.com/rustsbi/prototyper"
 

bench-kernel/src/main.rs

@@ -8,7 +8,10 @@ extern crate rcore_console;
 
 use core::mem::MaybeUninit;
 use core::sync::{atomic::AtomicBool, atomic::AtomicU64, atomic::Ordering};
-use core::{arch::asm, ptr::null};
+use core::{
+    arch::{asm, naked_asm},
+    ptr::null,
+};
 use log::*;
 use sbi::SbiRet;
 use sbi_spec::binary::{HartMask, MaskError};
@@ -16,8 +19,8 @@ use sbi_spec::hsm::hart_state;
 use sbi_testing::sbi;
 use serde::Deserialize;
 use serde_device_tree::{
-    buildin::{Node, NodeSeq, Reg, StrSeq},
     Dtb, DtbPtr,
+    buildin::{Node, NodeSeq, Reg, StrSeq},
 };
 use uart16550::Uart16550;
 
@@ -28,29 +31,30 @@ const RISCV_IMAGE_MAGIC2: u32 = 0x05435352; /* Magic number 2, little endian, "R
 
 /// boot header
 #[naked]
-#[no_mangle]
-#[link_section = ".head.text"]
+#[unsafe(no_mangle)]
+#[unsafe(link_section = ".head.text")]
 unsafe extern "C" fn _boot_header() -> ! {
-    asm!(
-        "j _start",
-        ".word 0",
-        ".balign 8",
-        ".dword 0x200000",
-        ".dword iend - istart",
-        ".dword {RISCV_HEAD_FLAGS}",
-        ".word  {RISCV_HEADER_VERSION}",
-        ".word  0",
-        ".dword 0",
-        ".dword {RISCV_IMAGE_MAGIC}",
-        ".balign 4",
-        ".word  {RISCV_IMAGE_MAGIC2}",
-        ".word  0",
-        RISCV_HEAD_FLAGS = const RISCV_HEAD_FLAGS,
-        RISCV_HEADER_VERSION = const RISCV_HEADER_VERSION,
-        RISCV_IMAGE_MAGIC = const RISCV_IMAGE_MAGIC,
-        RISCV_IMAGE_MAGIC2 = const RISCV_IMAGE_MAGIC2,
-        options(noreturn)
-    );
+    unsafe {
+        naked_asm!(
+            "j _start",
+            ".word 0",
+            ".balign 8",
+            ".dword 0x200000",
+            ".dword iend - istart",
+            ".dword {RISCV_HEAD_FLAGS}",
+            ".word  {RISCV_HEADER_VERSION}",
+            ".word  0",
+            ".dword 0",
+            ".dword {RISCV_IMAGE_MAGIC}",
+            ".balign 4",
+            ".word  {RISCV_IMAGE_MAGIC2}",
+            ".word  0",
+            RISCV_HEAD_FLAGS = const RISCV_HEAD_FLAGS,
+            RISCV_HEADER_VERSION = const RISCV_HEADER_VERSION,
+            RISCV_IMAGE_MAGIC = const RISCV_IMAGE_MAGIC,
+            RISCV_IMAGE_MAGIC2 = const RISCV_IMAGE_MAGIC2,
+        );
+    }
 }
 
 const STACK_SIZE: usize = 512 * 1024; // 512 KiB
@@ -67,16 +71,16 @@ impl HartStack {
     }
 }
 
-#[link_section = ".bss.uninit"]
+#[unsafe(link_section = ".bss.uninit")]
 static mut STACK: HartStack = HartStack::new();
-#[link_section = ".bss.uninit"]
+#[unsafe(link_section = ".bss.uninit")]
 static mut HART_STACK: [HartStack; MAX_HART_NUM] = [HartStack::new(); MAX_HART_NUM];
-#[link_section = ".bss.uninit"]
+#[unsafe(link_section = ".bss.uninit")]
 static mut IPI_SENT: [MaybeUninit<AtomicBool>; MAX_HART_NUM] =
     [const { MaybeUninit::uninit() }; MAX_HART_NUM];
-#[link_section = ".bss.uninit"]
+#[unsafe(link_section = ".bss.uninit")]
 static mut SMP_COUNT: usize = 0;
-#[link_section = ".bss.uninit"]
+#[unsafe(link_section = ".bss.uninit")]
 static mut BOOT_HART_ID: usize = 0;
 
 /// 内核入口。
@@ -85,49 +89,52 @@ static mut BOOT_HART_ID: usize = 0;
 ///
 /// 裸函数。
 #[naked]
-#[no_mangle]
-#[link_section = ".text.entry"]
+#[unsafe(no_mangle)]
+#[unsafe(link_section = ".text.entry")]
 unsafe extern "C" fn _start(hartid: usize, device_tree_paddr: usize) -> ! {
-    asm!(
-        // clear bss segment
-        "   la      t0, sbss
+    unsafe {
+        naked_asm!(
+            // clear bss segment
+            "   la      t0, sbss
             la      t1, ebss
         1:  bgeu    t0, t1, 2f
             sd      zero, 0(t0)
             addi    t0, t0, 8
             j       1b",
-        "2:",
-        "   la sp, {stack} + {stack_size}",
-        "   j  {main}",
-        stack_size = const STACK_SIZE,
-        stack      =   sym STACK,
-        main       =   sym rust_main,
-        options(noreturn),
-    )
+            "2:",
+            "   la sp, {stack} + {stack_size}",
+            "   j  {main}",
+            stack_size = const STACK_SIZE,
+            stack      =   sym STACK,
+            main       =   sym rust_main,
+        )
+    }
 }
 
 #[naked]
-#[no_mangle]
-unsafe extern "C" fn init_hart(hartid: usize, opaque: usize) {
-    asm!(
-        "add sp, a1, zero",
-        "csrw sscratch, sp",
-        "call {init_main}",
-        init_main = sym init_main,
-        options(noreturn),
-    )
+#[unsafe(no_mangle)]
+extern "C" fn init_hart(hartid: usize, opaque: usize) {
+    unsafe {
+        naked_asm!(
+            "add sp, a1, zero",
+            "csrw sscratch, sp",
+            "call {init_main}",
+            init_main = sym init_main,
+        )
+    }
 }
 
 #[naked]
-#[no_mangle]
-unsafe extern "C" fn core_send_ipi(hartid: usize, opaque: usize) {
-    asm!(
-        "add sp, a1, zero",
-        "csrw sscratch, sp",
-        "call {send_ipi}",
-        send_ipi = sym send_ipi,
-        options(noreturn),
-    )
+#[unsafe(no_mangle)]
+extern "C" fn core_send_ipi(hartid: usize, opaque: usize) {
+    unsafe {
+        naked_asm!(
+            "add sp, a1, zero",
+            "csrw sscratch, sp",
+            "call {send_ipi}",
+            send_ipi = sym send_ipi,
+        )
+    }
 }
 
 extern "C" fn send_ipi(hartid: usize) -> ! {

prototyper/Cargo.toml

@@ -9,20 +9,20 @@ repository.workspace = true
 forced-target = "riscv64imac-unknown-none-elf"
 
 [dependencies]
-aclint = "0.0.0"
-log = "0.4.21"
+aclint = "=0.1.0"
+log = "0.4"
 panic-halt = "1.0.0"
 riscv = "0.11.1"
-rustsbi = { version = "0.4.0", features = ["machine"] }
-sbi-spec = { version = "0.0.8", features = ["legacy"] }
-serde = { version = "1.0.202", default-features = false, features = ["derive"] }
 sifive-test-device = "0.0.0"
 spin = "0.9.8"
 uart16550 = "0.0.1"
 riscv-decode = "0.2.1"
 cfg-if = "1.0.0"
 buddy_system_allocator = "0.11.0"
-fast-trap = { version = "0.0.1", features = ["riscv-m"] }
+rustsbi = { version = "0.4.0", features = ["machine"] }
+sbi-spec = { version = "0.0.8", features = ["legacy"] }
+serde = { version = "1.0.202", default-features = false, features = ["derive"] }
+fast-trap = { version = "0.1.0",  features = ["riscv-m"] }
 serde-device-tree = { git = "https://github.com/rustsbi/serde-device-tree", default-features = false }
 uart_xilinx = { git = "https://github.com/duskmoon314/uart-rs/" }
 xuantie-riscv = { git= "https://github.com/rustsbi/xuantie" }

prototyper/src/devicetree.rs

@@ -1,7 +1,7 @@
 use serde::Deserialize;
 use serde_device_tree::{
-    buildin::{Node, NodeSeq, Reg, StrSeq},
     Dtb, DtbPtr,
+    buildin::{Node, NodeSeq, Reg, StrSeq},
 };
 
 use core::ops::Range;

prototyper/src/main.rs

@@ -19,14 +19,14 @@ mod platform;
 mod riscv;
 mod sbi;
 
-use core::arch::asm;
+use core::arch::{asm, naked_asm};
 
 use crate::platform::PLATFORM;
 use crate::riscv::csr::menvcfg;
 use crate::riscv::current_hartid;
 use crate::sbi::extensions::{
-    hart_extension_probe, hart_privileged_version, privileged_version_detection, Extension,
-    PrivilegedVersion,
+    Extension, PrivilegedVersion, hart_extension_probe, hart_privileged_version,
+    privileged_version_detection,
 };
 use crate::sbi::hart_context::NextStage;
 use crate::sbi::heap::sbi_heap_init;
@@ -37,7 +37,7 @@ use crate::sbi::trap_stack;
 
 pub const R_RISCV_RELATIVE: usize = 3;
 
-#[no_mangle]
+#[unsafe(no_mangle)]
 extern "C" fn rust_main(_hart_id: usize, opaque: usize, nonstandard_a2: usize) {
     // Track whether SBI is initialized and ready.
 
@@ -127,81 +127,84 @@ extern "C" fn rust_main(_hart_id: usize, opaque: usize, nonstandard_a2: usize) {
 }
 
 #[naked]
-#[link_section = ".text.entry"]
-#[export_name = "_start"]
+#[unsafe(link_section = ".text.entry")]
+#[unsafe(export_name = "_start")]
 unsafe extern "C" fn start() -> ! {
-    core::arch::asm!(
-        // 1. Turn off interrupt.
-        "   csrw    mie, zero",
-        // 2. Initialize programming language runtime.
-        // only clear bss if hartid matches preferred boot hart id.
-        "   csrr    t0, mhartid",
-        "   bne     t0, zero, 4f",
-        "   call    {relocation_update}",
-        "1:",
-        // 3. Hart 0 clear bss segment.
-        "   lla     t0, sbi_bss_start
+    unsafe {
+        naked_asm!(
+            ".option arch, +a",
+            // 1. Turn off interrupt.
+            "   csrw    mie, zero",
+            // 2. Initialize programming language runtime.
+            // only clear bss if hartid matches preferred boot hart id.
+            "   csrr    t0, mhartid",
+            "   bne     t0, zero, 4f",
+            "   call    {relocation_update}",
+            "1:",
+            // 3. Hart 0 clear bss segment.
+            "   lla     t0, sbi_bss_start
             lla     t1, sbi_bss_end
          2: bgeu    t0, t1, 3f
             sd      zero, 0(t0)
             addi    t0, t0, 8
             j       2b",
-        "3: ", // Hart 0 set bss ready signal.
-        "   lla     t0, 6f
+            "3: ", // Hart 0 set bss ready signal.
+            "   lla     t0, 6f
             li      t1, 1
             amoadd.w t0, t1, 0(t0)
             j       5f",
-        "4:", // Other harts are waiting for bss ready signal.
-        "   li      t1, 1
+            "4:", // Other harts are waiting for bss ready signal.
+            "   li      t1, 1
             lla     t0, 6f
             lw      t0, 0(t0)
             bne     t0, t1, 4b",
-        "5:",
-         // 4. Prepare stack for each hart.
-        "   call    {locate_stack}",
-        "   call    {main}",
-        "   csrw    mscratch, sp",
-        "   j       {hart_boot}",
-        "  .balign  4",
-        "6:",  // bss ready signal.
-        "  .word    0",
-        relocation_update = sym relocation_update,
-        locate_stack = sym trap_stack::locate,
-        main         = sym rust_main,
-        hart_boot    = sym trap::boot::boot,
-        options(noreturn)
-    )
+            "5:",
+             // 4. Prepare stack for each hart.
+            "   call    {locate_stack}",
+            "   call    {main}",
+            "   csrw    mscratch, sp",
+            "   j       {hart_boot}",
+            "  .balign  4",
+            "6:",  // bss ready signal.
+            "  .word    0",
+            relocation_update = sym relocation_update,
+            locate_stack = sym trap_stack::locate,
+            main         = sym rust_main,
+            hart_boot    = sym trap::boot::boot,
+        )
+    }
 }
 
 // Handle relocations for position-independent code
 #[naked]
 unsafe extern "C" fn relocation_update() {
-    asm!(
-        // Get load offset.
-        "   li t0, {START_ADDRESS}",
-        "   lla t1, sbi_start",
-        "   sub t2, t1, t0",
-
-        // Foreach rela.dyn and update relocation.
-        "   lla t0, __rel_dyn_start",
-        "   lla t1, __rel_dyn_end",
-        "   li  t3, {R_RISCV_RELATIVE}",
-        "1:",
-        "   ld  t4, 8(t0)",
-        "   bne t4, t3, 2f",
-        "   ld t4, 0(t0)", // Get offset
-        "   ld t5, 16(t0)", // Get append
-        "   add t4, t4, t2", // Add load offset to offset add append
-        "   add t5, t5, t2",
-        "   sd t5, 0(t4)", // Update address
-        "   addi t0, t0, 24", // Get next rela item
-        "2:",
-        "   blt t0, t1, 1b",
-
-        // Return
-        "   ret",
-        R_RISCV_RELATIVE = const R_RISCV_RELATIVE,
-        START_ADDRESS = const cfg::SBI_LINK_START_ADDRESS,
-        options(noreturn)
-    )
+    unsafe {
+        naked_asm!(
+            // Get load offset.
+            "   li t0, {START_ADDRESS}",
+            "   lla t1, sbi_start",
+            "   sub t2, t1, t0",
+
+            // Foreach rela.dyn and update relocation.
+            "   lla t0, __rel_dyn_start",
+            "   lla t1, __rel_dyn_end",
+            "   li  t3, {R_RISCV_RELATIVE}",
+            "1:",
+            "   ld  t4, 8(t0)",
+            "   bne t4, t3, 2f",
+            "   ld t4, 0(t0)", // Get offset
+            "   ld t5, 16(t0)", // Get append
+            "   add t4, t4, t2", // Add load offset to offset add append
+            "   add t5, t5, t2",
+            "   sd t5, 0(t4)", // Update address
+            "   addi t0, t0, 24", // Get next rela item
+            "2:",
+            "   blt t0, t1, 1b",
+
+            // Return
+            "   ret",
+            R_RISCV_RELATIVE = const R_RISCV_RELATIVE,
+            START_ADDRESS = const cfg::SBI_LINK_START_ADDRESS,
+        )
+    }
 }

prototyper/src/platform/console.rs

@@ -1,6 +1,6 @@
 use bouffalo_hal::uart::RegisterBlock as BflbUartRegisterBlock;
-use uart16550::{Register, Uart16550};
 use uart_xilinx::MmioUartAxiLite;
+use uart16550::{Register, Uart16550};
 
 use crate::sbi::console::ConsoleDevice;
 pub(crate) const UART16650U8_COMPATIBLE: [&str; 1] = ["ns16550a"];

prototyper/src/platform/mod.rs

@@ -16,10 +16,11 @@ use crate::platform::clint::{MachineClintType, SIFIVE_CLINT_COMPATIBLE, THEAD_CL
 use crate::platform::console::Uart16550Wrap;
 use crate::platform::console::UartBflbWrap;
 use crate::platform::console::{
-    MachineConsoleType, UART16650U32_COMPATIBLE, UART16650U8_COMPATIBLE, UARTAXILITE_COMPATIBLE,
+    MachineConsoleType, UART16650U8_COMPATIBLE, UART16650U32_COMPATIBLE, UARTAXILITE_COMPATIBLE,
     UARTBFLB_COMPATIBLE,
 };
 use crate::platform::reset::SIFIVETEST_COMPATIBLE;
+use crate::sbi::SBI;
 use crate::sbi::console::SbiConsole;
 use crate::sbi::extensions;
 use crate::sbi::hsm::SbiHsm;
@@ -28,7 +29,6 @@ use crate::sbi::logger;
 use crate::sbi::reset::SbiReset;
 use crate::sbi::rfence::SbiRFence;
 use crate::sbi::trap_stack;
-use crate::sbi::SBI;
 
 mod clint;
 mod console;

prototyper/src/sbi/early_trap.rs

@@ -1,4 +1,4 @@
-use core::arch::asm;
+use core::arch::naked_asm;
 
 /// When you expected some insts will cause trap, use this.
 /// If trap happened, a0 will set to 1, otherwise will be 0.
@@ -7,14 +7,15 @@ use core::arch::asm;
 #[naked]
 #[repr(align(16))]
 pub(crate) unsafe extern "C" fn expected_trap() {
-    asm!(
-        "add a0, zero, zero",
-        "add a1, zero, zero",
-        "csrr a1, mepc",
-        "addi a1, a1, 4",
-        "csrw mepc, a1",
-        "addi a0, zero, 1",
-        "mret",
-        options(noreturn)
-    )
+    unsafe {
+        naked_asm!(
+            "add a0, zero, zero",
+            "add a1, zero, zero",
+            "csrr a1, mepc",
+            "addi a1, a1, 4",
+            "csrw mepc, a1",
+            "addi a0, zero, 1",
+            "mret",
+        )
+    }
 }

prototyper/src/sbi/heap.rs

@@ -1,7 +1,7 @@
 use crate::cfg::HEAP_SIZE;
 use buddy_system_allocator::LockedHeap;
 
-#[link_section = ".bss.heap"]
+#[unsafe(link_section = ".bss.heap")]
 static mut HEAP: [u8; HEAP_SIZE] = [0; HEAP_SIZE];
 
 #[global_allocator]

prototyper/src/sbi/hsm.rs

@@ -4,7 +4,7 @@ use core::{
     sync::atomic::{AtomicUsize, Ordering},
 };
 use riscv::register::mstatus::MPP;
-use rustsbi::{spec::hsm::hart_state, SbiRet};
+use rustsbi::{SbiRet, spec::hsm::hart_state};
 
 use crate::platform::PLATFORM;
 use crate::riscv::current_hartid;

prototyper/src/sbi/ipi.rs

@@ -1,7 +1,7 @@
 use crate::platform::PLATFORM;
 use crate::riscv::csr::stimecmp;
 use crate::riscv::current_hartid;
-use crate::sbi::extensions::{hart_extension_probe, Extension};
+use crate::sbi::extensions::{Extension, hart_extension_probe};
 use crate::sbi::hsm::remote_hsm;
 use crate::sbi::rfence;
 use crate::sbi::trap_stack::ROOT_STACK;

prototyper/src/sbi/trap/boot.rs

@@ -1,7 +1,7 @@
 use crate::riscv::current_hartid;
 use crate::sbi::hsm::local_hsm;
 use crate::sbi::ipi;
-use core::arch::asm;
+use core::arch::naked_asm;
 use riscv::register::{mie, mstatus, satp, sstatus};
 
 /// Boot Function.
@@ -9,31 +9,32 @@ use riscv::register::{mie, mstatus, satp, sstatus};
 /// so we can store a0, a1 and mepc only.
 #[naked]
 pub unsafe extern "C" fn boot() -> ! {
-    asm!(
-        ".align 2",
-        // Switch stacks
-        "csrrw  sp, mscratch, sp",
-        // Allocate stack space
-        "addi   sp, sp, -3*8",
-        // Call handler with context pointer
-        "mv     a0, sp",
-        "call   {boot_handler}",
-        // Restore mepc
-        "ld     t0, 0*8(sp)
-        csrw    mepc, t0",
-        // Restore registers
-        "
+    unsafe {
+        naked_asm!(
+            ".align 2",
+            // Switch stacks
+            "csrrw  sp, mscratch, sp",
+            // Allocate stack space
+            "addi   sp, sp, -3*8",
+            // Call handler with context pointer
+            "mv     a0, sp",
+            "call   {boot_handler}",
+            // Restore mepc
+            "ld     t0, 0*8(sp)
+            csrw    mepc, t0",
+            // Restore registers
+            "
         ld      a0, 1*8(sp)
         ld      a1, 2*8(sp)",
-        // Restore stack pointer
-        "addi   sp, sp, 3*8",
-        // Switch stacks back
-        "csrrw  sp, mscratch, sp",
-        // Return from machine mode
-        "mret",
-        boot_handler = sym boot_handler,
-        options(noreturn)
-    );
+            // Restore stack pointer
+            "addi   sp, sp, 3*8",
+            // Switch stacks back
+            "csrrw  sp, mscratch, sp",
+            // Return from machine mode
+            "mret",
+            boot_handler = sym boot_handler,
+        );
+    }
 }
 
 /// Boot Handler.

prototyper/src/sbi/trap/handler.rs

@@ -149,7 +149,7 @@ pub fn delegate(ctx: &mut FastContext) {
 #[inline]
 pub fn illegal_instruction_handler(ctx: &mut FastContext) -> bool {
     use riscv::register::{mepc, mtval};
-    use riscv_decode::{decode, Instruction};
+    use riscv_decode::{Instruction, decode};
 
     let inst = decode(mtval::read() as u32);
     match inst {

prototyper/src/sbi/trap_stack.rs

@@ -6,7 +6,7 @@ use core::mem::forget;
 use fast_trap::FreeTrapStack;
 
 /// Root stack array for all harts, placed in BSS Stack section.
-#[link_section = ".bss.stack"]
+#[unsafe(link_section = ".bss.stack")]
 pub(crate) static mut ROOT_STACK: [Stack; NUM_HART_MAX] = [Stack::ZERO; NUM_HART_MAX];
 
 /// Locates and initializes stack for each hart.
@@ -14,8 +14,9 @@ pub(crate) static mut ROOT_STACK: [Stack; NUM_HART_MAX] = [Stack::ZERO; NUM_HART
 /// This is a naked function that sets up the stack pointer based on hart ID.
 #[naked]
 pub(crate) unsafe extern "C" fn locate() {
-    core::arch::asm!(
-        "   la   sp, {stack}            // Load stack base address
+    unsafe {
+        core::arch::naked_asm!(
+            "   la   sp, {stack}            // Load stack base address
             li   t0, {per_hart_stack_size} // Load stack size per hart
             csrr t1, mhartid            // Get current hart ID
             addi t1, t1,  1             // Add 1 to hart ID
@@ -25,11 +26,11 @@ pub(crate) unsafe extern "C" fn locate() {
             call t1, {move_stack}       // Call stack reuse function
             ret                         // Return
         ",
-        per_hart_stack_size = const LEN_STACK_PER_HART,
-        stack               =   sym ROOT_STACK,
-        move_stack          =   sym fast_trap::reuse_stack_for_trap,
-        options(noreturn),
-    )
+            per_hart_stack_size = const LEN_STACK_PER_HART,
+            stack               =   sym ROOT_STACK,
+            move_stack          =   sym fast_trap::reuse_stack_for_trap,
+        )
+    }
 }
 
 /// Prepares trap stack for current hart

rust-toolchain.toml

@@ -1,5 +1,5 @@
 [toolchain]
-channel = "nightly-2024-09-21"
-components = ["rustfmt", "llvm-tools-preview", "clippy"]
+channel = "nightly-2025-02-08"
+components = ["rustfmt", "llvm-tools-preview", "clippy", "rust-src"]
 targets = ["riscv64imac-unknown-none-elf"]
 profile = "minimal"

supervisor/build.rs

@@ -1,3 +1,5 @@
 fn main() {
-    println!("cargo:rustc-link-arg=-Ttarget/riscv64imac-unknown-none-elf/release/linker_riscv64-qemu-virt.lds");
+    println!(
+        "cargo:rustc-link-arg=-Ttarget/riscv64imac-unknown-none-elf/release/linker_riscv64-qemu-virt.lds"
+    );
 }

test-kernel/Cargo.toml

@@ -12,7 +12,7 @@ publish = false
 # See more keys and their definitions at https://doc.rust-lang.org/cargo/reference/manifest.html
 
 [dependencies]
-sbi-testing = { version = "0.0.3-alpha.2", features = ["log"] }
+sbi-testing = { git = "https://github.com/rustsbi/rustsbi" , features = ["log"] }
 log = "0.4"
 riscv = "0.11.1"
 spin = "0.9"

test-kernel/src/main.rs

@@ -6,7 +6,7 @@
 #[macro_use]
 extern crate rcore_console;
 
-use core::{arch::asm, ptr::null};
+use core::{arch::{asm, naked_asm} , ptr::null};
 use sbi_testing::sbi;
 use uart16550::Uart16550;
 
@@ -17,29 +17,30 @@ const RISCV_IMAGE_MAGIC2: u32 = 0x05435352; /* Magic number 2, little endian, "R
 
 /// boot header
 #[naked]
-#[no_mangle]
-#[link_section = ".head.text"]
+#[unsafe(no_mangle)]
+#[unsafe(link_section = ".head.text")]
 unsafe extern "C" fn _boot_header() -> ! {
-    asm!(
-        "j _start",
-        ".word 0",
-        ".balign 8",
-        ".dword 0x200000",
-        ".dword iend - istart",
-        ".dword {RISCV_HEAD_FLAGS}",
-        ".word  {RISCV_HEADER_VERSION}",
-        ".word  0",
-        ".dword 0",
-        ".dword {RISCV_IMAGE_MAGIC}",
-        ".balign 4",
-        ".word  {RISCV_IMAGE_MAGIC2}",
-        ".word  0",
-        RISCV_HEAD_FLAGS = const RISCV_HEAD_FLAGS,
-        RISCV_HEADER_VERSION = const RISCV_HEADER_VERSION,
-        RISCV_IMAGE_MAGIC = const RISCV_IMAGE_MAGIC,
-        RISCV_IMAGE_MAGIC2 = const RISCV_IMAGE_MAGIC2,
-        options(noreturn)
-    );
+    unsafe {
+        naked_asm!(
+            "j _start",
+            ".word 0",
+            ".balign 8",
+            ".dword 0x200000",
+            ".dword iend - istart",
+            ".dword {RISCV_HEAD_FLAGS}",
+            ".word  {RISCV_HEADER_VERSION}",
+            ".word  0",
+            ".dword 0",
+            ".dword {RISCV_IMAGE_MAGIC}",
+            ".balign 4",
+            ".word  {RISCV_IMAGE_MAGIC2}",
+            ".word  0",
+            RISCV_HEAD_FLAGS = const RISCV_HEAD_FLAGS,
+            RISCV_HEADER_VERSION = const RISCV_HEADER_VERSION,
+            RISCV_IMAGE_MAGIC = const RISCV_IMAGE_MAGIC,
+            RISCV_IMAGE_MAGIC2 = const RISCV_IMAGE_MAGIC2,
+        );
+    }
 }
 
 /// 内核入口。
@@ -48,30 +49,31 @@ unsafe extern "C" fn _boot_header() -> ! {
 ///
 /// 裸函数。
 #[naked]
-#[no_mangle]
-#[link_section = ".text.entry"]
+#[unsafe(no_mangle)]
+#[unsafe(link_section = ".text.entry")]
 unsafe extern "C" fn _start(hartid: usize, device_tree_paddr: usize) -> ! {
     const STACK_SIZE: usize = 16384; // 16 KiB
 
-    #[link_section = ".bss.uninit"]
+    #[unsafe(link_section = ".bss.uninit")]
     static mut STACK: [u8; STACK_SIZE] = [0u8; STACK_SIZE];
 
-    asm!(
-        // clear bss segment
-        "   la      t0, sbss
+    unsafe {
+        naked_asm!(
+            // clear bss segment
+            "   la      t0, sbss
             la      t1, ebss
         1:  bgeu    t0, t1, 2f
             sd      zero, 0(t0)
             addi    t0, t0, 8
             j       1b",
-        "2:",
-        "   la sp, {stack} + {stack_size}",
-        "   j  {main}",
-        stack_size = const STACK_SIZE,
-        stack      =   sym STACK,
-        main       =   sym rust_main,
-        options(noreturn),
-    )
+            "2:",
+            "   la sp, {stack} + {stack_size}",
+            "   j  {main}",
+            stack_size = const STACK_SIZE,
+            stack      =   sym STACK,
+            main       =   sym rust_main,
+        )
+    }
 }
 
 extern "C" fn rust_main(hartid: usize, dtb_pa: usize) -> ! {

xtask/src/bench.rs

@@ -47,10 +47,14 @@ pub fn run(arg: &BenchArg) -> Option<ExitStatus> {
         match fs::exists(target_dir.join("rustsbi-prototyper.bin")) {
             Ok(true) => {}
             Ok(false) => {
-                panic!(" Couldn't open \"rustsbi-prototyper.bin\": No such file or directory. Please compile Prototyper first");
+                panic!(
+                    " Couldn't open \"rustsbi-prototyper.bin\": No such file or directory. Please compile Prototyper first"
+                );
             }
             Err(_) => {
-                panic!("Can't check existence of file rustsbi-prototyper.bin, please compile Prototyper first");
+                panic!(
+                    "Can't check existence of file rustsbi-prototyper.bin, please compile Prototyper first"
+                );
             }
         }
         fs::copy(

xtask/src/prototyper.rs

@@ -5,8 +5,8 @@ use std::{
 
 use clap::Args;
 
-use crate::utils::cargo;
 use crate::utils::CmdOptional;
+use crate::utils::cargo;
 
 #[derive(Debug, Args, Clone)]
 pub struct PrototyperArg {

xtask/src/test.rs

@@ -47,10 +47,14 @@ pub fn run(arg: &TestArg) -> Option<ExitStatus> {
         match fs::exists(target_dir.join("rustsbi-prototyper.bin")) {
             Ok(true) => {}
             Ok(false) => {
-                panic!(" Couldn't open \"rustsbi-prototyper.bin\": No such file or directory. Please compile Prototyper first");
+                panic!(
+                    " Couldn't open \"rustsbi-prototyper.bin\": No such file or directory. Please compile Prototyper first"
+                );
             }
             Err(_) => {
-                panic!("Can't check existence of file rustsbi-prototyper.bin, please compile Prototyper first");
+                panic!(
+                    "Can't check existence of file rustsbi-prototyper.bin, please compile Prototyper first"
+                );
             }
         }
         fs::copy(