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+#![no_std]
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+#![no_main]
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+#![feature(naked_functions)]
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+#![deny(warnings)]
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+
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+#[macro_use]
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+extern crate rcore_console;
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+
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+use core::{arch::asm, ptr::null};
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+use sbi_testing::sbi;
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+use uart16550::Uart16550;
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+
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+/// 内核入口。
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+///
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+/// # Safety
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+///
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+/// 裸函数。
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+#[naked]
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+#[no_mangle]
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+#[link_section = ".text.entry"]
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+unsafe extern "C" fn _start(hartid: usize, device_tree_paddr: usize) -> ! {
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+ const STACK_SIZE: usize = 16384; // 16 KiB
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+
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+ #[link_section = ".bss.uninit"]
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+ static mut STACK: [u8; STACK_SIZE] = [0u8; STACK_SIZE];
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+
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+ asm!(
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+ // clear bss segment
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+ " la t0, sbss
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+ la t1, ebss
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+ 1: bgeu t0, t1, 2f
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+ sd zero, 0(t0)
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+ addi t0, t0, 8
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+ j 1b",
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+ "2:",
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+ " la sp, {stack} + {stack_size}",
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+ " j {main}",
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+ stack_size = const STACK_SIZE,
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+ stack = sym STACK,
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+ main = sym rust_main,
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+ options(noreturn),
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+ )
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+}
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+
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+extern "C" fn rust_main(hartid: usize, dtb_pa: usize) -> ! {
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+ let BoardInfo {
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+ smp,
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+ frequency,
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+ uart,
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+ } = BoardInfo::parse(dtb_pa);
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+ unsafe { UART = Uart16550Map(uart as _) };
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+ rcore_console::init_console(&Console);
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+ rcore_console::set_log_level(option_env!("LOG"));
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+ println!(
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+ r"
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+ _____ _ _ __ _
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+|_ _|__ ___| |_ | |/ /___ _ __ _ __ ___| |
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+ | |/ _ \/ __| __| | ' // _ \ '__| '_ \ / _ \ |
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+ | | __/\__ \ |_ | . \ __/ | | | | | __/ |
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+ |_|\___||___/\__| |_|\_\___|_| |_| |_|\___|_|
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+================================================
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+| boot hart id | {hartid:20} |
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+| smp | {smp:20} |
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+| timebase frequency | {frequency:17} Hz |
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+| dtb physical address | {dtb_pa:#20x} |
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+------------------------------------------------"
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+ );
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+ let testing = sbi_testing::Testing {
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+ hartid,
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+ hart_mask: (1 << smp) - 1,
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+ hart_mask_base: 0,
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+ delay: frequency,
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+ };
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+ if testing.test() {
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+ sbi::system_reset(sbi::Shutdown, sbi::NoReason);
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+ } else {
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+ sbi::system_reset(sbi::Shutdown, sbi::SystemFailure);
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+ }
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+ unreachable!()
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+}
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+
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+#[cfg_attr(not(test), panic_handler)]
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+fn panic(info: &core::panic::PanicInfo) -> ! {
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+ let (hart_id, pc): (usize, usize);
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+ unsafe { asm!("mv {}, tp", out(reg) hart_id) };
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+ unsafe { asm!("auipc {}, 0", out(reg) pc) };
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+ println!("[test-kernel-panic] hart {hart_id} {info}");
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+ println!("[test-kernel-panic] pc = {pc:#x}");
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+ println!("[test-kernel-panic] SBI test FAILED due to panic");
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+ sbi::system_reset(sbi::Shutdown, sbi::SystemFailure);
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+ loop {}
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+}
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+
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+struct BoardInfo {
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+ smp: usize,
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+ frequency: u64,
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+ uart: usize,
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+}
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+
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+impl BoardInfo {
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+ fn parse(dtb_pa: usize) -> Self {
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+ use dtb_walker::{Dtb, DtbObj, HeaderError as E, Property, Str, WalkOperation::*};
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+
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+ let mut ans = Self {
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+ smp: 0,
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+ frequency: 0,
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+ uart: 0,
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+ };
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+ unsafe {
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+ Dtb::from_raw_parts_filtered(dtb_pa as _, |e| {
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+ matches!(e, E::Misaligned(4) | E::LastCompVersion(_))
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+ })
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+ }
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+ .unwrap()
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+ .walk(|ctx, obj| match obj {
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+ DtbObj::SubNode { name } => {
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+ if ctx.is_root() && (name == Str::from("cpus") || name == Str::from("soc")) {
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+ StepInto
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+ } else if ctx.name() == Str::from("cpus") && name.starts_with("cpu@") {
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+ ans.smp += 1;
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+ StepOver
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+ } else if ctx.name() == Str::from("soc")
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+ && (name.starts_with("uart") || name.starts_with("serial"))
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+ {
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+ StepInto
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+ } else {
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+ StepOver
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+ }
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+ }
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+ DtbObj::Property(Property::Reg(mut reg)) => {
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+ if ctx.name().starts_with("uart") || ctx.name().starts_with("serial") {
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+ ans.uart = reg.next().unwrap().start;
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+ }
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+ StepOut
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+ }
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+ DtbObj::Property(Property::General { name, value }) => {
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+ if ctx.name() == Str::from("cpus") && name == Str::from("timebase-frequency") {
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+ ans.frequency = match *value {
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+ [a, b, c, d] => u32::from_be_bytes([a, b, c, d]) as _,
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+ [a, b, c, d, e, f, g, h] => u64::from_be_bytes([a, b, c, d, e, f, g, h]),
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+ _ => unreachable!(),
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+ };
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+ }
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+ StepOver
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+ }
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+ DtbObj::Property(_) => StepOver,
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+ });
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+ ans
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+ }
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+}
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+
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+struct Console;
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+static mut UART: Uart16550Map = Uart16550Map(null());
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+
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+pub struct Uart16550Map(*const Uart16550<u8>);
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+
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+unsafe impl Sync for Uart16550Map {}
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+
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+impl Uart16550Map {
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+ #[inline]
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+ pub fn get(&self) -> &Uart16550<u8> {
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+ unsafe { &*self.0 }
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+ }
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+}
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+
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+impl rcore_console::Console for Console {
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+ #[inline]
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+ fn put_char(&self, c: u8) {
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+ unsafe { UART.get().write(core::slice::from_ref(&c)) };
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+ }
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+
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+ #[inline]
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+ fn put_str(&self, s: &str) {
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+ unsafe { UART.get().write(s.as_bytes()) };
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+ }
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+}
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guttatus