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@@ -0,0 +1,1112 @@
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+use alloc::collections::BTreeMap;
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+use alloc::vec::Vec;
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+use riscv::register::*;
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+use rustsbi::{Pmu, SbiRet};
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+use sbi_spec::binary::SharedPtr;
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+use sbi_spec::pmu::shmem_size::SIZE;
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+use sbi_spec::pmu::*;
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+
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+use crate::riscv::csr::*;
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+use crate::{riscv::current_hartid, sbi::features::hart_mhpm_mask};
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+
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+use super::features::{PrivilegedVersion, hart_privileged_version};
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+use super::trap_stack::{hart_context, hart_context_mut};
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+
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+/// Maximum number of hardware performance counters supported.
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+const PMU_HARDWARE_COUNTER_MAX: usize = 32;
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+/// Maximum number of firmware-managed counters supported.
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+const PMU_FIRMWARE_COUNTER_MAX: usize = 16;
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+/// Marker value for inactive/invalid event indices.
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+const PMU_EVENT_IDX_INVALID: usize = usize::MAX;
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+
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+/// PMU state tracking hardware and firmware performance counters
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+#[repr(C)]
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+pub struct PmuState {
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+ active_event: [usize; PMU_HARDWARE_COUNTER_MAX + PMU_FIRMWARE_COUNTER_MAX],
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+ /// Bitmap of active firmware counters (1 bit per counter)
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+ fw_counter_state: usize,
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+ /// Values for firmware-managed counters
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+ fw_counter: [u64; PMU_FIRMWARE_COUNTER_MAX],
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+ hw_counters_num: usize,
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+ total_counters_num: usize,
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+}
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+
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+impl PmuState {
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+ /// Creates a new PMU state with default configuration.
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+ pub fn new() -> Self {
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+ let mhpm_mask = hart_mhpm_mask(current_hartid());
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+ let hw_counters_num = mhpm_mask.count_ones() as usize;
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+ let total_counters_num = hw_counters_num + PMU_FIRMWARE_COUNTER_MAX;
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+
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+ let mut active_event =
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+ [PMU_EVENT_IDX_INVALID; PMU_HARDWARE_COUNTER_MAX + PMU_FIRMWARE_COUNTER_MAX];
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+ // Standard mappings for fixed counters
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+ active_event[1] = 0x0; // time (memory-mapped)
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+
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+ Self {
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+ active_event,
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+ fw_counter_state: 0,
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+ fw_counter: [0; PMU_FIRMWARE_COUNTER_MAX],
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+ hw_counters_num,
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+ total_counters_num,
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+ }
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+ }
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+
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+ /// Returns the number of hardware counters available.
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+ #[inline(always)]
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+ pub fn get_hw_counter_num(&self) -> usize {
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+ self.hw_counters_num
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+ }
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+
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+ /// Returns the total number of counters (hardware + firmware).
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+ #[inline(always)]
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+ pub fn get_total_counters_num(&self) -> usize {
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+ self.total_counters_num
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+ }
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+
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+ /// Gets the event index associated with a counter.
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+ #[inline]
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+ pub fn get_event_idx(&self, counter_idx: usize, firmware_event: bool) -> Option<EventIdx> {
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+ if counter_idx >= self.total_counters_num {
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+ return None;
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+ }
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+ if firmware_event && counter_idx < self.hw_counters_num {
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+ return None;
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+ }
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+
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+ Some(EventIdx::new(self.active_event[counter_idx]))
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+ }
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+
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+ /// Gets the value of a firmware counter.
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+ #[inline]
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+ pub fn get_fw_counter(&self, counter_idx: usize) -> Option<u64> {
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+ if counter_idx < self.hw_counters_num || counter_idx >= self.total_counters_num {
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+ return None;
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+ }
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+ let fw_idx = counter_idx - self.hw_counters_num;
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+ // Safety: fw_idx is guaranteed to be within bounds (0..FIRMWARE_COUNTER_MAX)
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+ unsafe { Some(*self.fw_counter.get_unchecked(fw_idx)) }
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+ }
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+
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+ /// start a firmware counter with a optional new value.
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+ #[inline]
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+ fn start_fw_counter(
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+ &mut self,
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+ counter_idx: usize,
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+ initial_value: u64,
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+ is_update_value: bool,
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+ ) -> Result<(), StartCounterErr> {
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+ if counter_idx < self.hw_counters_num || counter_idx >= self.total_counters_num {
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+ return Err(StartCounterErr::OffsetInvalid);
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+ }
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+ let fw_idx = counter_idx - self.hw_counters_num;
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+
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+ if self.fw_counter_state & (1 << fw_idx) != 0 {
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+ return Err(StartCounterErr::AlreadyStart);
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+ }
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+
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+ if is_update_value {
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+ self.fw_counter[fw_idx] = initial_value;
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+ }
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+ self.fw_counter_state |= 1 << fw_idx; // Mark as active
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+ Ok(())
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+ }
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+
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+ /// stop a firmware counter
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+ #[inline]
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+ fn stop_fw_counter(
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+ &mut self,
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+ counter_idx: usize,
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+ is_reset: bool,
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+ ) -> Result<(), StopCounterErr> {
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+ if counter_idx < self.hw_counters_num || counter_idx >= self.total_counters_num {
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+ return Err(StopCounterErr::OffsetInvalid);
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+ }
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+ let fw_idx = counter_idx - self.hw_counters_num;
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+
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+ if self.fw_counter_state & (1 << fw_idx) == 0 {
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+ return Err(StopCounterErr::AlreadyStop);
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+ }
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+
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+ if is_reset {
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+ self.active_event[counter_idx] = PMU_EVENT_IDX_INVALID;
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+ }
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+ self.fw_counter_state &= !(1 << fw_idx); // Mark as stop
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+ Ok(())
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+ }
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+
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+ #[inline]
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+ pub fn is_firmware_event_start(&self, counter_idx: usize) -> bool {
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+ if counter_idx < self.hw_counters_num || counter_idx >= self.total_counters_num {
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+ return false;
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+ }
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+ let fw_idx = counter_idx - self.hw_counters_num;
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+ self.fw_counter_state & (1 << fw_idx) != 0
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+ }
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+}
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+
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+pub struct SbiPmu {
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+ event_to_mhpmevent: Option<BTreeMap<u32, u64>>,
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+ event_to_mhpmcounter: Option<Vec<EventToCounterMap>>,
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+ raw_event_to_mhpmcounter: Option<Vec<RawEventToCounterMap>>,
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+}
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+
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+impl Pmu for SbiPmu {
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+ /// Returns the total number of available performance counters
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+ ///
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+ /// Implements SBI PMU extension function (FID #0)
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+ #[inline]
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+ fn num_counters(&self) -> usize {
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+ hart_context(current_hartid())
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+ .pmu_state
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+ .get_total_counters_num()
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+ }
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+
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+ /// DONE:
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+ /// Function: Get details of a counter (FID #1)
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+ #[inline]
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+ fn counter_get_info(&self, counter_idx: usize) -> SbiRet {
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+ if counter_idx >= self.num_counters() {
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+ return SbiRet::invalid_param();
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+ }
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+
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+ let pmu_state = &hart_context(current_hartid()).pmu_state;
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+ if counter_idx < pmu_state.get_hw_counter_num() {
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+ let mask = hart_mhpm_mask(current_hartid());
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+
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+ // Find the corresponding hardware counter using bit manipulation
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+ // This is more efficient than iterating through all possible offsets
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+ let mut remaining_mask = mask;
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+ let mut count = 0;
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+
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+ while remaining_mask != 0 {
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+ if count == counter_idx {
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+ // Found the counter - get its CSR offset
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+ let offset = remaining_mask.trailing_zeros() as u16;
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+ return SbiRet::success(
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+ CounterInfo::with_hardware_info(CSR_CYCLE + offset, 63).inner(),
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+ );
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+ }
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+ remaining_mask &= remaining_mask - 1;
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+ count += 1;
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+ }
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+ return SbiRet::invalid_param();
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+ }
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+
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+ SbiRet::success(CounterInfo::with_firmware_info().inner())
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+ }
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+
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+ /// Find and configure a matching counter (FID #2)
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+ #[inline]
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+ fn counter_config_matching(
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+ &self,
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+ counter_idx_base: usize,
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+ counter_idx_mask: usize,
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+ config_flags: usize,
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+ event_idx: usize,
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+ event_data: u64,
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+ ) -> SbiRet {
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+ let flags = match flags::CounterCfgFlags::from_bits(config_flags) {
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+ Some(flags) => flags,
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+ None => return SbiRet::invalid_param(), // Reserved bits are set
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+ };
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+
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+ let event = EventIdx::new(event_idx);
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+ let pmu_state = &mut hart_context_mut(current_hartid()).pmu_state;
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+ let is_firmware_event = event.is_firmware_event();
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+
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+ if counter_idx_base >= pmu_state.total_counters_num
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+ || (counter_idx_mask & ((1 << pmu_state.total_counters_num) - 1)) == 0
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+ || !event.check_event_type()
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+ || (is_firmware_event && !event.firmware_event_valid())
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+ {
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+ return SbiRet::invalid_param();
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+ }
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+
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+ let skip_match = flags.contains(flags::CounterCfgFlags::SKIP_MATCH);
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+
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+ let counter_idx;
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+
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+ if skip_match {
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+ // If SKIP_MATCH is set, use the first counter in the mask without searching
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+ if let Some(ctr_idx) = CounterMask::new(counter_idx_base, counter_idx_mask).next() {
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+ if pmu_state.active_event[ctr_idx] == PMU_EVENT_IDX_INVALID {
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+ return SbiRet::invalid_param();
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+ }
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+ counter_idx = ctr_idx;
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+ } else {
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+ return SbiRet::invalid_param();
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+ }
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+ } else {
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+ let match_result: Result<usize, SbiRet>;
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+ if event.is_firmware_event() {
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+ match_result = self.find_firmware_counter(
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+ counter_idx_base,
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+ counter_idx_mask,
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+ event_idx,
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+ pmu_state,
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+ );
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+ } else {
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+ match_result = self.find_hardware_counter(
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+ counter_idx_base,
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+ counter_idx_mask,
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+ event_idx,
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+ event_data,
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+ pmu_state,
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+ );
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+ }
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+ match match_result {
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+ Ok(ctr_idx) => {
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+ counter_idx = ctr_idx;
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+ }
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+ Err(err) => {
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+ return err;
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+ }
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+ }
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+ pmu_state.active_event[counter_idx] = event_idx;
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+ }
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+
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+ if configure_counter(pmu_state, counter_idx, event, flags) {
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+ return SbiRet::success(counter_idx);
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+ }
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+
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+ return SbiRet::not_supported();
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+ }
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+
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+ /// Start one or more counters (FID #3)
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+ /// Note: The next two functions contain redundant logic and should be refactored.
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+ #[inline]
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+ fn counter_start(
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+ &self,
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+ counter_idx_base: usize,
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+ counter_idx_mask: usize,
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+ start_flags: usize,
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+ initial_value: u64,
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+ ) -> SbiRet {
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+ let flags = match flags::CounterStartFlags::from_bits(start_flags) {
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+ Some(flags) => flags,
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+ None => return SbiRet::invalid_param(),
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+ };
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+
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+ let pmu_state = &mut hart_context_mut(current_hartid()).pmu_state;
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+ let is_update_value = flags.contains(flags::CounterStartFlags::INIT_VALUE);
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+
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+ if counter_idx_base >= pmu_state.total_counters_num
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+ || (counter_idx_mask & ((1 << pmu_state.total_counters_num) - 1)) == 0
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+ {
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+ return SbiRet::invalid_param();
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+ }
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+
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+ if flags.contains(flags::CounterStartFlags::INIT_SNAPSHOT) {
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+ return SbiRet::no_shmem();
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+ }
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+
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+ for counter_idx in CounterMask::new(counter_idx_base, counter_idx_mask) {
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+ if counter_idx >= pmu_state.total_counters_num {
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+ return SbiRet::invalid_param();
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+ }
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+
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+ let start_result = if counter_idx >= pmu_state.get_hw_counter_num() {
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+ pmu_state.start_fw_counter(counter_idx, initial_value, is_update_value)
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+ } else {
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+ let mhpm_offset = get_mhpm_csr_offset(counter_idx).unwrap();
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+ start_hardware_counter(mhpm_offset, initial_value, is_update_value)
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+ };
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+ match start_result {
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+ Ok(_) => {}
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+ Err(StartCounterErr::AlreadyStart) => {
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+ return SbiRet::already_started();
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+ }
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+ Err(StartCounterErr::OffsetInvalid) => {
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+ return SbiRet::invalid_param();
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+ }
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+ }
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+ }
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+ SbiRet::success(0)
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+ }
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+
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+ /// Stop one or more counters (FID #4)
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+ #[inline]
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+ fn counter_stop(
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+ &self,
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+ counter_idx_base: usize,
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+ counter_idx_mask: usize,
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+ stop_flags: usize,
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+ ) -> SbiRet {
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+ let flags = match flags::CounterStopFlags::from_bits(stop_flags) {
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+ Some(flags) => flags,
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+ None => return SbiRet::invalid_param(),
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+ };
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+
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+ let pmu_state = &mut hart_context_mut(current_hartid()).pmu_state;
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+ let is_reset = flags.contains(flags::CounterStopFlags::RESET);
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+
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+ if counter_idx_base >= pmu_state.total_counters_num
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+ || (counter_idx_mask & ((1 << pmu_state.total_counters_num) - 1)) == 0
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+ {
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+ return SbiRet::invalid_param();
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+ }
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+
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+ if flags.contains(flags::CounterStopFlags::TAKE_SNAPSHOT) {
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+ return SbiRet::no_shmem();
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+ }
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+
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+ for counter_idx in CounterMask::new(counter_idx_base, counter_idx_mask) {
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+ if counter_idx >= pmu_state.total_counters_num {
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+ return SbiRet::invalid_param();
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+ }
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+
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+ let stop_result = if counter_idx >= pmu_state.get_hw_counter_num() {
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+ pmu_state.stop_fw_counter(counter_idx, is_reset)
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+ } else {
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+ // If RESET flag is set, mark the counter as inactive
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+ if is_reset {
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+ pmu_state.active_event[counter_idx] = PMU_EVENT_IDX_INVALID;
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+ }
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+ let mhpm_offset = get_mhpm_csr_offset(counter_idx).unwrap();
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+ stop_hardware_counter(mhpm_offset, is_reset)
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+ };
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+ match stop_result {
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+ Ok(_) => {}
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+ Err(StopCounterErr::OffsetInvalid) => return SbiRet::invalid_param(),
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+ Err(StopCounterErr::AlreadyStop) => return SbiRet::already_stopped(),
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+ }
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+ }
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+ SbiRet::success(0)
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+ }
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+
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+ /// Reads a firmware counter value
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+ /// Function: Read a firmware counter (FID #5).
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+ #[inline]
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+ fn counter_fw_read(&self, counter_idx: usize) -> SbiRet {
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+ let pmu_state = &hart_context(current_hartid()).pmu_state;
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+ match pmu_state.get_event_idx(counter_idx, true) {
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+ Some(event_id) if event_id.firmware_event_valid() => {
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+ if event_id.event_code() == firmware_event::PLATFORM {
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+ // TODO: Handle platform-specific PMU events
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+ return SbiRet::invalid_param();
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+ }
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+ match pmu_state.get_fw_counter(counter_idx) {
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+ Some(value) => SbiRet::success(value as usize),
|
|
|
+ None => SbiRet::invalid_param(),
|
|
|
+ }
|
|
|
+ }
|
|
|
+ _ => SbiRet::invalid_param(),
|
|
|
+ }
|
|
|
+ }
|
|
|
+
|
|
|
+ /// Function: Read a firmware counter high bits (FID #6).
|
|
|
+ #[inline]
|
|
|
+ fn counter_fw_read_hi(&self, _counter_idx: usize) -> SbiRet {
|
|
|
+ // The Specification states the this function always return zero in sbiret.value for RV64 (or higher) systems.
|
|
|
+ // Currently RustSBI Prototyper only supports RV64 systems
|
|
|
+ SbiRet::success(0)
|
|
|
+ }
|
|
|
+
|
|
|
+ /// Function: Set PMU snapshot shared memory (FID #7).
|
|
|
+ #[inline]
|
|
|
+ fn snapshot_set_shmem(&self, shmem: SharedPtr<[u8; SIZE]>, flags: usize) -> SbiRet {
|
|
|
+ // Optional function, `not_supported` is returned if not implemented.
|
|
|
+ let _ = (shmem, flags);
|
|
|
+ SbiRet::not_supported()
|
|
|
+ }
|
|
|
+}
|
|
|
+
|
|
|
+impl Default for SbiPmu {
|
|
|
+ fn default() -> Self {
|
|
|
+ Self {
|
|
|
+ event_to_mhpmevent: None,
|
|
|
+ event_to_mhpmcounter: None,
|
|
|
+ raw_event_to_mhpmcounter: None,
|
|
|
+ }
|
|
|
+ }
|
|
|
+}
|
|
|
+
|
|
|
+impl SbiPmu {
|
|
|
+ fn find_firmware_counter(
|
|
|
+ &self,
|
|
|
+ counter_idx_base: usize,
|
|
|
+ counter_idx_mask: usize,
|
|
|
+ event_idx: usize,
|
|
|
+ pmu_state: &PmuState,
|
|
|
+ ) -> Result<usize, SbiRet> {
|
|
|
+ // TODO: support `PLATFORM` event
|
|
|
+ let event = EventIdx::new(event_idx);
|
|
|
+ if !event.firmware_event_valid() {
|
|
|
+ return Err(SbiRet::not_supported());
|
|
|
+ }
|
|
|
+
|
|
|
+ // TODO: If all firmware events are implemented,
|
|
|
+ // this condition should be removed.
|
|
|
+ if event.event_code() <= 21 {
|
|
|
+ if !PMU_FIRMWARE_EVENT_SUPPORTED[event.event_code()] {
|
|
|
+ return Err(SbiRet::not_supported());
|
|
|
+ }
|
|
|
+ }
|
|
|
+
|
|
|
+ for counter_idx in CounterMask::new(counter_idx_base, counter_idx_mask) {
|
|
|
+ // If counter idx is not a firmware counter index, skip this index
|
|
|
+ if counter_idx < pmu_state.get_hw_counter_num()
|
|
|
+ || counter_idx >= pmu_state.get_total_counters_num()
|
|
|
+ {
|
|
|
+ continue;
|
|
|
+ }
|
|
|
+ // If the firmware counter at this index is already occupied, skip this index
|
|
|
+ if pmu_state.active_event[counter_idx] != PMU_EVENT_IDX_INVALID {
|
|
|
+ continue;
|
|
|
+ }
|
|
|
+ return Ok(counter_idx);
|
|
|
+ }
|
|
|
+ return Err(SbiRet::not_supported());
|
|
|
+ }
|
|
|
+
|
|
|
+ fn find_hardware_counter(
|
|
|
+ &self,
|
|
|
+ counter_idx_base: usize,
|
|
|
+ counter_idx_mask: usize,
|
|
|
+ event_idx: usize,
|
|
|
+ event_data: u64,
|
|
|
+ pmu_state: &PmuState,
|
|
|
+ ) -> Result<usize, SbiRet> {
|
|
|
+ let event = EventIdx::new(event_idx);
|
|
|
+ let mut hw_counters_mask = 0;
|
|
|
+ // Find the counters available for the event.
|
|
|
+ if event.is_raw_event() {
|
|
|
+ if let Some(ref raw_event_map_vec) = self.raw_event_to_mhpmcounter {
|
|
|
+ for raw_event_map in raw_event_map_vec {
|
|
|
+ if raw_event_map.have_event(event_data) {
|
|
|
+ hw_counters_mask = raw_event_map.get_counter_mask();
|
|
|
+ break;
|
|
|
+ }
|
|
|
+ }
|
|
|
+ } else {
|
|
|
+ return Err(SbiRet::not_supported());
|
|
|
+ }
|
|
|
+ } else {
|
|
|
+ // event is general event or cache event
|
|
|
+ if let Some(ref sbi_hw_event_map_vec) = self.event_to_mhpmcounter {
|
|
|
+ for sbi_hw_event_map in sbi_hw_event_map_vec {
|
|
|
+ if sbi_hw_event_map.have_event(event_idx as u32) {
|
|
|
+ hw_counters_mask = sbi_hw_event_map.get_counter_mask();
|
|
|
+ break;
|
|
|
+ }
|
|
|
+ }
|
|
|
+ } else {
|
|
|
+ return Err(SbiRet::not_supported());
|
|
|
+ }
|
|
|
+ }
|
|
|
+ // mcycle, time, minstret cannot be used for other events.
|
|
|
+ let mhpm_mask = hart_mhpm_mask(current_hartid());
|
|
|
+ let can_use_counter_mask = hw_counters_mask & mhpm_mask;
|
|
|
+
|
|
|
+ // Find a counter that meets the conditions from a set of counters
|
|
|
+ for counter_idx in CounterMask::new(counter_idx_base, counter_idx_mask) {
|
|
|
+ if counter_idx >= pmu_state.hw_counters_num {
|
|
|
+ continue;
|
|
|
+ }
|
|
|
+
|
|
|
+ // If the counter idx corresponding to the hardware counter index cannot be used by the event,
|
|
|
+ // or has already been used, skip this counter idx
|
|
|
+ let mhpm_offset = get_mhpm_csr_offset(counter_idx).unwrap();
|
|
|
+ // Find a unused counter
|
|
|
+ if (can_use_counter_mask >> mhpm_offset) & 0x1 == 0
|
|
|
+ || pmu_state.active_event[counter_idx] != PMU_EVENT_IDX_INVALID
|
|
|
+ {
|
|
|
+ continue;
|
|
|
+ }
|
|
|
+ // If mcycle is selected but the event is not SBI_PMU_HW_CPU_CYCLES,
|
|
|
+ // or minstret is selected but the event is not SBI_PMU_HW_INSTRUCTIONS, skip
|
|
|
+ if (mhpm_offset == 0 && event_idx != 1) || (mhpm_offset == 2 && event_idx != 2) {
|
|
|
+ continue;
|
|
|
+ }
|
|
|
+ // If the counter idx corresponding to the hardware counter index has already started counting, skip the counter
|
|
|
+ if hart_privileged_version(current_hartid()) >= PrivilegedVersion::Version1_11 {
|
|
|
+ let inhibit = riscv::register::mcountinhibit::read();
|
|
|
+ if (inhibit.bits() & (1 << mhpm_offset)) == 0 {
|
|
|
+ continue;
|
|
|
+ }
|
|
|
+ }
|
|
|
+
|
|
|
+ // Found a counter that meets the conditions - write the event value to the corresponding mhpmevent
|
|
|
+ self.pmu_update_hardware_mhpmevent(mhpm_offset, event_idx, event_data)?;
|
|
|
+ return Ok(counter_idx);
|
|
|
+ }
|
|
|
+ Err(SbiRet::not_supported())
|
|
|
+ }
|
|
|
+
|
|
|
+ fn pmu_update_hardware_mhpmevent(
|
|
|
+ &self,
|
|
|
+ mhpm_offset: u16,
|
|
|
+ event_idx: usize,
|
|
|
+ event_data: u64,
|
|
|
+ ) -> Result<(), SbiRet> {
|
|
|
+ // If the event is SBI_PMU_HW_CPU_CYCLES and mcycle is selected,
|
|
|
+ // or the event is SBI_PMU_HW_INSTRUCTIONS and minstret is selected, return directly
|
|
|
+ if (mhpm_offset == 0 && event_idx == 1) || (mhpm_offset == 2 && event_idx == 2) {
|
|
|
+ return Ok(());
|
|
|
+ }
|
|
|
+ // Validate counter offset range (only mhpmcounter3-31 are configurable)
|
|
|
+ if mhpm_offset == 1 || mhpm_offset > 31 {
|
|
|
+ return Err(SbiRet::not_supported());
|
|
|
+ }
|
|
|
+
|
|
|
+ let event = EventIdx::new(event_idx);
|
|
|
+
|
|
|
+ // Determine the value to write to mhpmevent CSR
|
|
|
+ let mhpmevent_val = if event.is_raw_event() {
|
|
|
+ // For raw events, use the provided event_data directly
|
|
|
+ event_data
|
|
|
+ } else if let Some(ref event_to_mhpmevent) = self.event_to_mhpmevent {
|
|
|
+ // For standard events, look up the corresponding mhpmevent value
|
|
|
+ *event_to_mhpmevent
|
|
|
+ .get(&(event_idx as u32))
|
|
|
+ .ok_or(SbiRet::not_supported())?
|
|
|
+ } else if self.event_to_mhpmcounter.is_some() {
|
|
|
+ // Handle QEMU compatibility case:
|
|
|
+ // When only event_to_mhpmcounter is available (like in QEMU),
|
|
|
+ // use the event index directly as the raw event value
|
|
|
+ event_idx as u64
|
|
|
+ } else {
|
|
|
+ // No mapping available for this event
|
|
|
+ return Err(SbiRet::not_supported());
|
|
|
+ };
|
|
|
+
|
|
|
+ write_mhpmevent(mhpm_offset, mhpmevent_val);
|
|
|
+ Ok(())
|
|
|
+ }
|
|
|
+
|
|
|
+ pub fn insert_event_to_mhpmevent(&mut self, event: u32, mhpmevent: u64) {
|
|
|
+ let event_to_mhpmevent_map = self.event_to_mhpmevent.get_or_insert_default();
|
|
|
+
|
|
|
+ //TODO: When https://github.com/rust-lang/rust/issues/82766 is stable, change this to `try_insert`
|
|
|
+ if let Some(mhpmevent_mapped) = event_to_mhpmevent_map.get(&event) {
|
|
|
+ error!(
|
|
|
+ "Try to map event:0x{:08x} to mhpmevent:0x{:016x}, but the event has been mapped to mhpmevent:{}, please check the device tree file",
|
|
|
+ event, mhpmevent, mhpmevent_mapped
|
|
|
+ );
|
|
|
+ } else {
|
|
|
+ event_to_mhpmevent_map.insert(event, mhpmevent);
|
|
|
+ }
|
|
|
+ }
|
|
|
+
|
|
|
+ pub fn insert_event_to_mhpmcounter(&mut self, event_to_counter: EventToCounterMap) {
|
|
|
+ let event_to_mhpmcounter_map = self.event_to_mhpmcounter.get_or_insert_default();
|
|
|
+ for event_to_mhpmcounter in event_to_mhpmcounter_map.iter() {
|
|
|
+ if event_to_mhpmcounter.is_overlop(&event_to_counter) {
|
|
|
+ error!(
|
|
|
+ "The mapping of event_to_mhpmcounter {:?} and {:?} overlap, please check the device tree file",
|
|
|
+ event_to_mhpmcounter, event_to_counter
|
|
|
+ );
|
|
|
+ return;
|
|
|
+ }
|
|
|
+ }
|
|
|
+ event_to_mhpmcounter_map.push(event_to_counter);
|
|
|
+ }
|
|
|
+
|
|
|
+ pub fn insert_raw_event_to_mhpmcounter(&mut self, raw_event_to_counter: RawEventToCounterMap) {
|
|
|
+ let raw_event_to_mhpmcounter_map = self.raw_event_to_mhpmcounter.get_or_insert_default();
|
|
|
+ for raw_event_to_mhpmcounter in raw_event_to_mhpmcounter_map.iter() {
|
|
|
+ if raw_event_to_mhpmcounter.is_overlop(&raw_event_to_counter) {
|
|
|
+ error!(
|
|
|
+ "The mapping of raw_event_to_mhpmcounter {:?} and {:?} overlap, please check the device tree file",
|
|
|
+ raw_event_to_mhpmcounter, raw_event_to_counter
|
|
|
+ );
|
|
|
+ return;
|
|
|
+ }
|
|
|
+ }
|
|
|
+ raw_event_to_mhpmcounter_map.push(raw_event_to_counter);
|
|
|
+ }
|
|
|
+}
|
|
|
+
|
|
|
+/// Configures a counter to monitor an event based on the given flags.
|
|
|
+///
|
|
|
+/// Returns `true` if configuration succeeds, `false` otherwise.
|
|
|
+#[inline]
|
|
|
+fn configure_counter(
|
|
|
+ pmu_state: &mut PmuState,
|
|
|
+ counter_idx: usize,
|
|
|
+ event: EventIdx,
|
|
|
+ flags: flags::CounterCfgFlags,
|
|
|
+) -> bool {
|
|
|
+ let auto_start = flags.contains(flags::CounterCfgFlags::AUTO_START);
|
|
|
+ let clear_value = flags.contains(flags::CounterCfgFlags::CLEAR_VALUE);
|
|
|
+ if event.is_firmware_event() {
|
|
|
+ let firmware_event_idx = counter_idx - pmu_state.hw_counters_num;
|
|
|
+ if clear_value {
|
|
|
+ pmu_state.fw_counter[firmware_event_idx] = 0;
|
|
|
+ }
|
|
|
+ if auto_start {
|
|
|
+ pmu_state.fw_counter_state |= 1 << firmware_event_idx;
|
|
|
+ }
|
|
|
+ } else {
|
|
|
+ let mhpm_offset = get_mhpm_csr_offset(counter_idx).unwrap();
|
|
|
+ if clear_value {
|
|
|
+ write_mhpmcounter(mhpm_offset, 0);
|
|
|
+ }
|
|
|
+ if auto_start {
|
|
|
+ return start_hardware_counter(mhpm_offset, 0, false).is_ok();
|
|
|
+ }
|
|
|
+ }
|
|
|
+ true
|
|
|
+}
|
|
|
+
|
|
|
+/// Get the offset of the mhpmcounter CSR corresponding to counter_idx relative to mcycle
|
|
|
+fn get_mhpm_csr_offset(counter_idx: usize) -> Option<u16> {
|
|
|
+ let mhpm_mask = hart_mhpm_mask(current_hartid());
|
|
|
+ let mut count = 0;
|
|
|
+ for offset in 0..32 {
|
|
|
+ if (mhpm_mask >> offset) & 1 == 1 {
|
|
|
+ if count == counter_idx {
|
|
|
+ return Some(offset as u16);
|
|
|
+ }
|
|
|
+ count += 1;
|
|
|
+ }
|
|
|
+ }
|
|
|
+ None
|
|
|
+}
|
|
|
+
|
|
|
+/// Start Hardware Counter
|
|
|
+enum StartCounterErr {
|
|
|
+ OffsetInvalid,
|
|
|
+ AlreadyStart,
|
|
|
+}
|
|
|
+
|
|
|
+/// Starts a hardware performance counter specified by the offset.
|
|
|
+fn start_hardware_counter(
|
|
|
+ mhpm_offset: u16,
|
|
|
+ new_value: u64,
|
|
|
+ is_update_value: bool,
|
|
|
+) -> Result<(), StartCounterErr> {
|
|
|
+ if mhpm_offset == 1 || mhpm_offset > 31 {
|
|
|
+ return Err(StartCounterErr::OffsetInvalid);
|
|
|
+ }
|
|
|
+
|
|
|
+ if hart_privileged_version(current_hartid()) < PrivilegedVersion::Version1_11 {
|
|
|
+ if is_update_value {
|
|
|
+ write_mhpmcounter(mhpm_offset, new_value);
|
|
|
+ }
|
|
|
+ return Ok(());
|
|
|
+ }
|
|
|
+
|
|
|
+ // Check if counter is already running by testing the inhibit bit
|
|
|
+ // A zero bit in mcountinhibit means the counter is running
|
|
|
+ if mcountinhibit::read().bits() & (1 << mhpm_offset) == 0 {
|
|
|
+ return Err(StartCounterErr::AlreadyStart);
|
|
|
+ }
|
|
|
+
|
|
|
+ if is_update_value {
|
|
|
+ write_mhpmcounter(mhpm_offset, new_value);
|
|
|
+ }
|
|
|
+
|
|
|
+ unsafe {
|
|
|
+ match mhpm_offset {
|
|
|
+ 0 => mcountinhibit::clear_cy(),
|
|
|
+ 2 => mcountinhibit::clear_ir(),
|
|
|
+ _ => mcountinhibit::clear_hpm(mhpm_offset as usize),
|
|
|
+ }
|
|
|
+ }
|
|
|
+ Ok(())
|
|
|
+}
|
|
|
+
|
|
|
+/// Stop Hardware Counter
|
|
|
+enum StopCounterErr {
|
|
|
+ OffsetInvalid,
|
|
|
+ AlreadyStop,
|
|
|
+}
|
|
|
+
|
|
|
+/// Stops a hardware performance counter specified by the offset.
|
|
|
+fn stop_hardware_counter(mhpm_offset: u16, is_reset: bool) -> Result<(), StopCounterErr> {
|
|
|
+ if mhpm_offset == 1 || mhpm_offset > 31 {
|
|
|
+ return Err(StopCounterErr::OffsetInvalid);
|
|
|
+ }
|
|
|
+
|
|
|
+ if is_reset && mhpm_offset >= 3 && mhpm_offset <= 31 {
|
|
|
+ write_mhpmevent(mhpm_offset, 0);
|
|
|
+ }
|
|
|
+
|
|
|
+ if hart_privileged_version(current_hartid()) < PrivilegedVersion::Version1_11 {
|
|
|
+ return Ok(());
|
|
|
+ }
|
|
|
+
|
|
|
+ if mcountinhibit::read().bits() & (1 << mhpm_offset) != 0 {
|
|
|
+ return Err(StopCounterErr::AlreadyStop);
|
|
|
+ }
|
|
|
+
|
|
|
+ unsafe {
|
|
|
+ match mhpm_offset {
|
|
|
+ 0 => mcountinhibit::set_cy(),
|
|
|
+ 2 => mcountinhibit::set_ir(),
|
|
|
+ _ => mcountinhibit::set_hpm(mhpm_offset as usize),
|
|
|
+ }
|
|
|
+ }
|
|
|
+ Ok(())
|
|
|
+}
|
|
|
+
|
|
|
+/// Write MHPMEVENT or MHPMCOUNTER
|
|
|
+fn write_mhpmevent(mhpm_offset: u16, mhpmevent_val: u64) {
|
|
|
+ let csr = CSR_MHPMEVENT3 + mhpm_offset - 3;
|
|
|
+
|
|
|
+ // Handle MHPMEVENT3-31
|
|
|
+ if csr >= CSR_MHPMEVENT3 && csr <= CSR_MHPMEVENT31 {
|
|
|
+ // Convert CSR value to register index (3-31)
|
|
|
+ let idx = csr - CSR_MHPMEVENT3 + 3;
|
|
|
+
|
|
|
+ // Use seq_macro to generate all valid indices from 3 to 31
|
|
|
+ seq_macro::seq!(N in 3..=31 {
|
|
|
+ match idx {
|
|
|
+ #(
|
|
|
+ N => pastey::paste!{ [<mhpmevent ~N>]::write(mhpmevent_val as usize) },
|
|
|
+ )*
|
|
|
+ _ =>{}
|
|
|
+ }
|
|
|
+ });
|
|
|
+ }
|
|
|
+}
|
|
|
+
|
|
|
+fn write_mhpmcounter(mhpm_offset: u16, mhpmcounter_val: u64) {
|
|
|
+ let counter_idx = mhpm_offset;
|
|
|
+
|
|
|
+ let csr = CSR_MHPMCOUNTER3 + mhpm_offset - 3;
|
|
|
+ // Special cases for cycle and instret
|
|
|
+ if csr == CSR_MCYCLE {
|
|
|
+ crate::riscv::csr::mcycle::write(mhpmcounter_val);
|
|
|
+ return;
|
|
|
+ } else if csr == CSR_MINSTRET {
|
|
|
+ crate::riscv::csr::minstret::write(mhpmcounter_val);
|
|
|
+ return;
|
|
|
+ }
|
|
|
+
|
|
|
+ // Only handle valid counter indices (3-31)
|
|
|
+ if counter_idx >= 3 && counter_idx <= 31 {
|
|
|
+ // Call the macro with all valid indices
|
|
|
+ seq_macro::seq!(N in 3..=31 {
|
|
|
+ match counter_idx {
|
|
|
+ #(
|
|
|
+ N => pastey::paste!{ [<mhpmcounter ~N>]::write(mhpmcounter_val as usize) },
|
|
|
+ )*
|
|
|
+ _ =>{}
|
|
|
+ }
|
|
|
+ });
|
|
|
+ }
|
|
|
+}
|
|
|
+
|
|
|
+/// Wrap for counter info
|
|
|
+struct CounterInfo {
|
|
|
+ /// Packed representation of counter information:
|
|
|
+ /// - Bits [11:0]: CSR number for hardware counters
|
|
|
+ /// - Bits [17:12]: Counter width (typically 63 for RV64)
|
|
|
+ /// - MSB: Set for firmware counters, clear for hardware counters
|
|
|
+ inner: usize,
|
|
|
+}
|
|
|
+
|
|
|
+#[allow(unused)]
|
|
|
+impl CounterInfo {
|
|
|
+ const CSR_MASK: usize = 0xFFF; // Bits [11:0]
|
|
|
+ const WIDTH_MASK: usize = 0x3F << 12; // Bits [17:12]
|
|
|
+ const FIRMWARE_FLAG: usize = 1 << (size_of::<usize>() * 8 - 1); // MSB
|
|
|
+
|
|
|
+ #[inline]
|
|
|
+ pub const fn new() -> Self {
|
|
|
+ Self { inner: 0 }
|
|
|
+ }
|
|
|
+
|
|
|
+ #[inline]
|
|
|
+ pub fn set_csr(&mut self, csr_num: u16) {
|
|
|
+ self.inner = (self.inner & !Self::CSR_MASK) | ((csr_num as usize) & Self::CSR_MASK);
|
|
|
+ }
|
|
|
+
|
|
|
+ #[inline]
|
|
|
+ pub fn set_width(&mut self, width: u8) {
|
|
|
+ self.inner = (self.inner & !Self::WIDTH_MASK) | (((width as usize) & 0x3F) << 12);
|
|
|
+ }
|
|
|
+
|
|
|
+ #[inline]
|
|
|
+ pub const fn with_hardware_info(csr_num: u16, width: u8) -> Self {
|
|
|
+ Self {
|
|
|
+ inner: ((csr_num as usize) & Self::CSR_MASK) | (((width as usize) & 0x3F) << 12),
|
|
|
+ }
|
|
|
+ }
|
|
|
+
|
|
|
+ #[inline]
|
|
|
+ pub const fn with_firmware_info() -> Self {
|
|
|
+ Self {
|
|
|
+ inner: Self::FIRMWARE_FLAG,
|
|
|
+ }
|
|
|
+ }
|
|
|
+
|
|
|
+ #[inline]
|
|
|
+ pub const fn inner(self) -> usize {
|
|
|
+ self.inner
|
|
|
+ }
|
|
|
+}
|
|
|
+
|
|
|
+impl Default for CounterInfo {
|
|
|
+ #[inline]
|
|
|
+ fn default() -> Self {
|
|
|
+ Self::new()
|
|
|
+ }
|
|
|
+}
|
|
|
+
|
|
|
+#[derive(Clone, Copy)]
|
|
|
+pub struct EventIdx {
|
|
|
+ /// Packed representation of event information:
|
|
|
+ /// - Bits [15:0]: Event code
|
|
|
+ /// - Bits [19:16]: Event type
|
|
|
+ inner: usize,
|
|
|
+}
|
|
|
+
|
|
|
+#[allow(unused)]
|
|
|
+impl EventIdx {
|
|
|
+ #[inline]
|
|
|
+ const fn new(event_idx: usize) -> Self {
|
|
|
+ Self { inner: event_idx }
|
|
|
+ }
|
|
|
+
|
|
|
+ #[inline]
|
|
|
+ fn from_firmwarw_event(firmware_event: usize) -> Self {
|
|
|
+ Self {
|
|
|
+ inner: 0xf << 16 | firmware_event,
|
|
|
+ }
|
|
|
+ }
|
|
|
+
|
|
|
+ #[inline]
|
|
|
+ fn raw(&self) -> usize {
|
|
|
+ self.inner
|
|
|
+ }
|
|
|
+
|
|
|
+ #[inline]
|
|
|
+ const fn event_type(&self) -> usize {
|
|
|
+ (self.inner >> 16) & 0xF
|
|
|
+ }
|
|
|
+
|
|
|
+ #[inline]
|
|
|
+ const fn event_code(&self) -> usize {
|
|
|
+ self.inner & 0xFFFF
|
|
|
+ }
|
|
|
+
|
|
|
+ /// Extracts the cache ID for HARDWARE_CACHE events (13 bits, [15:3])
|
|
|
+ #[inline]
|
|
|
+ const fn cache_id(&self) -> usize {
|
|
|
+ (self.inner >> 3) & 0x1FFF
|
|
|
+ }
|
|
|
+
|
|
|
+ /// Extracts the cache operation ID (2 bits, [2:1])
|
|
|
+ #[inline]
|
|
|
+ const fn cache_op_id(&self) -> usize {
|
|
|
+ (self.inner >> 1) & 0x3
|
|
|
+ }
|
|
|
+
|
|
|
+ /// Extracts the cache result ID (1 bit, [0])
|
|
|
+ #[inline]
|
|
|
+ const fn cache_result_id(&self) -> usize {
|
|
|
+ self.inner & 0x1
|
|
|
+ }
|
|
|
+
|
|
|
+ #[inline]
|
|
|
+ const fn is_general_event(&self) -> bool {
|
|
|
+ self.event_type() == event_type::HARDWARE_GENERAL
|
|
|
+ }
|
|
|
+
|
|
|
+ #[inline]
|
|
|
+ const fn is_cache_event(&self) -> bool {
|
|
|
+ self.event_type() == event_type::HARDWARE_CACHE
|
|
|
+ }
|
|
|
+
|
|
|
+ #[inline]
|
|
|
+ const fn is_raw_event_v1(&self) -> bool {
|
|
|
+ self.event_type() == event_type::HARDWARE_RAW
|
|
|
+ }
|
|
|
+
|
|
|
+ #[inline]
|
|
|
+ const fn is_raw_event_v2(&self) -> bool {
|
|
|
+ self.event_type() == event_type::HARDWARE_RAW_V2
|
|
|
+ }
|
|
|
+
|
|
|
+ #[inline]
|
|
|
+ const fn is_raw_event(&self) -> bool {
|
|
|
+ self.is_raw_event_v1() || self.is_raw_event_v2()
|
|
|
+ }
|
|
|
+
|
|
|
+ #[inline]
|
|
|
+ const fn is_firmware_event(&self) -> bool {
|
|
|
+ self.event_type() == event_type::FIRMWARE
|
|
|
+ }
|
|
|
+
|
|
|
+ #[inline]
|
|
|
+ fn check_event_type(self) -> bool {
|
|
|
+ let event_type = self.event_type();
|
|
|
+ let event_code = self.event_code();
|
|
|
+
|
|
|
+ match event_type {
|
|
|
+ event_type::HARDWARE_GENERAL => event_code <= hardware_event::REF_CPU_CYCLES,
|
|
|
+ event_type::HARDWARE_CACHE => {
|
|
|
+ self.cache_id() <= cache_event::NODE
|
|
|
+ && self.cache_op_id() <= cache_operation::PREFETCH
|
|
|
+ && self.cache_result_id() <= cache_result::MISS
|
|
|
+ }
|
|
|
+ event_type::HARDWARE_RAW | event_type::HARDWARE_RAW_V2 => event_code == 0,
|
|
|
+ event_type::FIRMWARE => true,
|
|
|
+ _ => false,
|
|
|
+ }
|
|
|
+ }
|
|
|
+
|
|
|
+ #[inline]
|
|
|
+ fn firmware_event_valid(self) -> bool {
|
|
|
+ let event_type = self.event_type();
|
|
|
+ let event_code = self.event_code();
|
|
|
+ if event_type != event_type::FIRMWARE {
|
|
|
+ return false;
|
|
|
+ }
|
|
|
+ if (event_code > firmware_event::HFENCE_VVMA_ASID_RECEIVED
|
|
|
+ && event_code < firmware_event::PLATFORM)
|
|
|
+ || event_code >= firmware_event::PLATFORM
|
|
|
+ {
|
|
|
+ // TODO:Currently RustSBI Prototyper does not support PLATFORM practice
|
|
|
+ return false;
|
|
|
+ }
|
|
|
+ true
|
|
|
+ }
|
|
|
+}
|
|
|
+
|
|
|
+/// event to mhpmcounter map
|
|
|
+#[derive(Debug)]
|
|
|
+pub struct EventToCounterMap {
|
|
|
+ counters_mask: u32, // Bitmask of supported counters
|
|
|
+ event_start_idx: u32, // Start of event code range
|
|
|
+ event_end_idx: u32, // End of event code range
|
|
|
+}
|
|
|
+
|
|
|
+impl EventToCounterMap {
|
|
|
+ pub fn new(counters_mask: u32, event_start_idx: u32, event_end_idx: u32) -> Self {
|
|
|
+ Self {
|
|
|
+ counters_mask,
|
|
|
+ event_start_idx,
|
|
|
+ event_end_idx,
|
|
|
+ }
|
|
|
+ }
|
|
|
+
|
|
|
+ #[inline]
|
|
|
+ pub const fn have_event(&self, event_idx: u32) -> bool {
|
|
|
+ event_idx >= self.event_start_idx && event_idx <= self.event_end_idx
|
|
|
+ }
|
|
|
+
|
|
|
+ #[inline]
|
|
|
+ pub fn get_counter_mask(&self) -> u32 {
|
|
|
+ self.counters_mask
|
|
|
+ }
|
|
|
+
|
|
|
+ #[inline]
|
|
|
+ pub fn is_overlop(&self, other_map: &EventToCounterMap) -> bool {
|
|
|
+ if (self.event_end_idx < other_map.event_start_idx
|
|
|
+ && self.event_end_idx < other_map.event_end_idx)
|
|
|
+ || (self.event_start_idx > other_map.event_start_idx
|
|
|
+ && self.event_start_idx > other_map.event_end_idx)
|
|
|
+ {
|
|
|
+ return false;
|
|
|
+ }
|
|
|
+ true
|
|
|
+ }
|
|
|
+}
|
|
|
+
|
|
|
+#[derive(Debug)]
|
|
|
+pub struct RawEventToCounterMap {
|
|
|
+ counters_mask: u32, // Bitmask of supported counters
|
|
|
+ raw_event_select: u64, // Value to program into mhpmeventX
|
|
|
+ select_mask: u64, // Mask for selecting bits (optional use)
|
|
|
+}
|
|
|
+
|
|
|
+impl RawEventToCounterMap {
|
|
|
+ pub fn new(counters_mask: u32, raw_event_select: u64, select_mask: u64) -> Self {
|
|
|
+ Self {
|
|
|
+ counters_mask,
|
|
|
+ raw_event_select,
|
|
|
+ select_mask,
|
|
|
+ }
|
|
|
+ }
|
|
|
+
|
|
|
+ #[inline]
|
|
|
+ pub const fn have_event(&self, event_idx: u64) -> bool {
|
|
|
+ self.raw_event_select == (event_idx & self.select_mask)
|
|
|
+ }
|
|
|
+
|
|
|
+ #[inline]
|
|
|
+ pub const fn get_counter_mask(&self) -> u32 {
|
|
|
+ self.counters_mask
|
|
|
+ }
|
|
|
+
|
|
|
+ #[inline]
|
|
|
+ pub const fn is_overlop(&self, other_map: &RawEventToCounterMap) -> bool {
|
|
|
+ self.select_mask == other_map.select_mask
|
|
|
+ && self.raw_event_select == other_map.raw_event_select
|
|
|
+ }
|
|
|
+}
|
|
|
+
|
|
|
+struct CounterMask {
|
|
|
+ counter_idx_base: usize,
|
|
|
+ counter_idx_mask: usize,
|
|
|
+}
|
|
|
+
|
|
|
+impl CounterMask {
|
|
|
+ pub fn new(counter_idx_base: usize, counter_idx_mask: usize) -> Self {
|
|
|
+ Self {
|
|
|
+ counter_idx_base,
|
|
|
+ counter_idx_mask,
|
|
|
+ }
|
|
|
+ }
|
|
|
+}
|
|
|
+
|
|
|
+impl Iterator for CounterMask {
|
|
|
+ type Item = usize;
|
|
|
+
|
|
|
+ fn next(&mut self) -> Option<Self::Item> {
|
|
|
+ if self.counter_idx_mask == 0 {
|
|
|
+ return None;
|
|
|
+ } else {
|
|
|
+ let low_bit = self.counter_idx_mask.trailing_zeros();
|
|
|
+ let hart_id = usize::try_from(low_bit).unwrap() + self.counter_idx_base;
|
|
|
+ self.counter_idx_mask &= !(1usize << low_bit);
|
|
|
+ Some(hart_id)
|
|
|
+ }
|
|
|
+ }
|
|
|
+}
|
|
|
+
|
|
|
+// TODO: If all firmware events are implemented,
|
|
|
+// `PMU_FIRMWARE_EVENT_SUPPORTED` should be removed.
|
|
|
+const PMU_FIRMWARE_EVENT_SUPPORTED: [bool; 22] = [
|
|
|
+ true, // SBI_PMU_FW_MISALIGNED_LOAD
|
|
|
+ true, // SBI_PMU_FW_MISALIGNED_STORE
|
|
|
+ false, // SBI_PMU_FW_ACCESS_LOAD
|
|
|
+ false, // SBI_PMU_FW_ACCESS_STORE
|
|
|
+ true, // SBI_PMU_FW_ILLEGAL_INSN
|
|
|
+ true, // SBI_PMU_FW_SET_TIMER
|
|
|
+ true, // SBI_PMU_FW_IPI_SENT
|
|
|
+ true, // SBI_PMU_FW_IPI_RECEIVED
|
|
|
+ true, // SBI_PMU_FW_FENCE_I_SENT
|
|
|
+ true, // SBI_PMU_FW_FENCE_I_RECEIVED
|
|
|
+ true, // SBI_PMU_FW_SFENCE_VMA_SENT
|
|
|
+ true, // SBI_PMU_FW_SFENCE_VMA_RECEIVED
|
|
|
+ true, // SBI_PMU_FW_SFENCE_VMA_ASID_SENT
|
|
|
+ true, // SBI_PMU_FW_SFENCE_VMA_ASID_RECEIVED
|
|
|
+ false, // SBI_PMU_FW_HFENCE_GVMA_SENT
|
|
|
+ false, // SBI_PMU_FW_HFENCE_GVMA_RECEIVED
|
|
|
+ false, // SBI_PMU_FW_HFENCE_GVMA_VMID_SENT
|
|
|
+ false, // SBI_PMU_FW_HFENCE_GVMA_VMID_RECEIVED
|
|
|
+ false, // SBI_PMU_FW_HFENCE_VVMA_SENT
|
|
|
+ false, // SBI_PMU_FW_HFENCE_VVMA_RECEIVED
|
|
|
+ false, // SBI_PMU_FW_HFENCE_VVMA_ASID_SENT
|
|
|
+ false, // SBI_PMU_FW_HFENCE_VVMA_ASID_RECEIVED
|
|
|
+];
|
|
|
+
|
|
|
+pub fn pmu_firmware_counter_increment(firmware_event: usize) {
|
|
|
+ let pmu_state = &mut hart_context_mut(current_hartid()).pmu_state;
|
|
|
+ let counter_idx_start = pmu_state.hw_counters_num;
|
|
|
+ for counter_idx in counter_idx_start..counter_idx_start + PMU_FIRMWARE_COUNTER_MAX {
|
|
|
+ let fw_idx = counter_idx - counter_idx_start;
|
|
|
+ if pmu_state.active_event[counter_idx]
|
|
|
+ == EventIdx::from_firmwarw_event(firmware_event).raw()
|
|
|
+ && pmu_state.is_firmware_event_start(counter_idx)
|
|
|
+ {
|
|
|
+ pmu_state.fw_counter[fw_idx] += 1;
|
|
|
+ }
|
|
|
+ }
|
|
|
+}
|
Luo Jia / Zhouqi Jiang