feat(prototyper): Added `riscv,isa` attributes

prototyper/src/board.rs

@@ -126,7 +126,6 @@ impl Board {
     }
 
     fn info_init(&mut self, dtb: &RefCell<Dtb>) {
-        // TODO: should remove `fail:device_tree_deserialize`.
         let root: serde_device_tree::buildin::Node = serde_device_tree::from_raw_mut(&dtb)
             .unwrap_or_else(fail::device_tree_deserialize_root);
         let tree: dt::Tree = root.deserialize();

prototyper/src/dt.rs

@@ -40,6 +40,8 @@ pub struct Cpus<'a> {
 pub struct Cpu<'a> {
     /// RISC-V ISA extensions supported by this CPU.
     #[serde(rename = "riscv,isa-extensions")]
+    pub isa_extensions: Option<StrSeq<'a>>,
+    #[serde(rename = "riscv,isa")]
     pub isa: Option<StrSeq<'a>>,
     /// CPU register information.
     pub reg: Reg<'a>,

prototyper/src/sbi/extensions.rs

@@ -40,10 +40,18 @@ pub fn init(cpus: &NodeSeq) {
         let cpu = cpu_iter.deserialize::<Cpu>();
         let hart_id = cpu.reg.iter().next().unwrap().0.start;
         let mut hart_exts = [false; Extension::COUNT];
-        let isa = cpu.isa.unwrap();
-        Extension::ITER.iter().for_each(|ext| {
-            hart_exts[ext.index()] = isa.iter().any(|e| e == ext.as_str());
-        });
+        if cpu.isa_extensions.is_some() {
+            let isa = cpu.isa_extensions.unwrap();
+            Extension::ITER.iter().for_each(|ext| {
+                hart_exts[ext.index()] = isa.iter().any(|e| e == ext.as_str());
+            });
+        } else if cpu.isa.is_some() {
+            let isa_iter = cpu.isa.unwrap();
+            let isa = isa_iter.iter().next().unwrap_or_default();
+            Extension::ITER.iter().for_each(|ext| {
+                hart_exts[ext.index()] = isa.find(ext.as_str()).is_some();
+            })
+        }
 
         unsafe {
             ROOT_STACK