Support RISC-V SBI Specification v0.3

CHANGELOG.md

@@ -6,6 +6,7 @@ and this project adheres to [Semantic Versioning](https://semver.org/spec/v2.0.0
 
 ## [0.2.0] - 2021-02-23
 ### Added
+- Support for RISC-V SBI v0.3 Specification
 - S-level Illegal instruction exception is now delegated into S-level software handler
 - Support RFENCE extension in RustSBI framework
 - Added a test kernel to test SBI function on RustSBI implementations

src/lib.rs

@@ -161,7 +161,7 @@ mod pmu;
 mod util;
 
 const SBI_SPEC_MAJOR: usize = 0;
-const SBI_SPEC_MINOR: usize = 2;
+const SBI_SPEC_MINOR: usize = 3;
 
 // RustSBI implementation ID: 4
 // Ref: https://github.com/riscv/riscv-sbi-doc/pull/61