Merge pull request #44 from woshiluo/priv_detect

feat(prototyper): Added support for Milk-V Duo 256M development board

.cargo/config.toml

@@ -2,3 +2,4 @@
 xtask = "run --package xtask --release --"
 prototyper = "xtask prototyper"
 test-kernel = "xtask test"
+bench-kernel = "xtask bench"

Cargo.lock

@@ -200,6 +200,12 @@ version = "0.2.0"
 source = "registry+https://github.com/rust-lang/crates.io-index"
 checksum = "de96540e0ebde571dc55c73d60ef407c653844e6f9a1e2fdbd40c07b9252d812"
 
+[[package]]
+name = "paste"
+version = "1.0.15"
+source = "registry+https://github.com/rust-lang/crates.io-index"
+checksum = "57c0d7b74b563b49d38dae00a0c37d4d6de9b432382b2892f0574ddcae73fd0a"
+
 [[package]]
 name = "proc-macro2"
 version = "1.0.92"
@@ -238,21 +244,54 @@ dependencies = [
  "embedded-hal",
 ]
 
+[[package]]
+name = "riscv"
+version = "0.12.1"
+source = "registry+https://github.com/rust-lang/crates.io-index"
+checksum = "5ea8ff73d3720bdd0a97925f0bf79ad2744b6da8ff36be3840c48ac81191d7a7"
+dependencies = [
+ "critical-section",
+ "embedded-hal",
+ "paste",
+ "riscv-pac",
+]
+
 [[package]]
 name = "riscv-decode"
 version = "0.2.2"
 source = "registry+https://github.com/rust-lang/crates.io-index"
 checksum = "cf8b4cfb0da0528321d22daee4299a23a8c5ac8848623d716e898d2a9eec0694"
 
+[[package]]
+name = "riscv-pac"
+version = "0.2.0"
+source = "registry+https://github.com/rust-lang/crates.io-index"
+checksum = "8188909339ccc0c68cfb5a04648313f09621e8b87dc03095454f1a11f6c5d436"
+
 [[package]]
 name = "rustsbi"
 version = "0.4.0"
 source = "registry+https://github.com/rust-lang/crates.io-index"
 checksum = "44c13763120794ed11d64bac885fb31d384ae385c3287b0697711b97affbf8ab"
 dependencies = [
- "riscv",
+ "riscv 0.11.1",
  "rustsbi-macros",
- "sbi-spec",
+ "sbi-spec 0.0.7",
+]
+
+[[package]]
+name = "rustsbi-bench-kernel"
+version = "0.0.0"
+dependencies = [
+ "log",
+ "rcore-console",
+ "riscv 0.11.1",
+ "sbi-spec 0.0.8",
+ "sbi-testing 0.0.3-alpha.2 (git+https://github.com/rustsbi/rustsbi?rev=4821073)",
+ "serde",
+ "serde-device-tree",
+ "spin",
+ "uart16550",
 ]
 
 [[package]]
@@ -274,10 +313,10 @@ dependencies = [
  "fast-trap",
  "log",
  "panic-halt",
- "riscv",
+ "riscv 0.11.1",
  "riscv-decode",
  "rustsbi",
- "sbi-spec",
+ "sbi-spec 0.0.7",
  "serde",
  "serde-device-tree",
  "sifive-test-device",
@@ -291,7 +330,7 @@ name = "rustsbi-supervisor"
 version = "0.1.0"
 dependencies = [
  "naked-function",
- "sbi-rt",
+ "sbi-rt 0.0.3 (registry+https://github.com/rust-lang/crates.io-index)",
 ]
 
 [[package]]
@@ -301,8 +340,8 @@ dependencies = [
  "dtb-walker",
  "log",
  "rcore-console",
- "riscv",
- "sbi-testing",
+ "riscv 0.11.1",
+ "sbi-testing 0.0.3-alpha.2 (registry+https://github.com/rust-lang/crates.io-index)",
  "spin",
  "uart16550",
 ]
@@ -313,7 +352,15 @@ version = "0.0.3"
 source = "registry+https://github.com/rust-lang/crates.io-index"
 checksum = "7fbaa69be1eedc61c426e6d489b2260482e928b465360576900d52d496a58bd0"
 dependencies = [
- "sbi-spec",
+ "sbi-spec 0.0.7",
+]
+
+[[package]]
+name = "sbi-rt"
+version = "0.0.3"
+source = "git+https://github.com/rustsbi/rustsbi?rev=4821073#4821073b56a7223781c11a49aba743785d89d3ea"
+dependencies = [
+ "sbi-spec 0.0.8",
 ]
 
 [[package]]
@@ -322,6 +369,14 @@ version = "0.0.7"
 source = "registry+https://github.com/rust-lang/crates.io-index"
 checksum = "e6e36312fb5ddc10d08ecdc65187402baba4ac34585cb9d1b78522ae2358d890"
 
+[[package]]
+name = "sbi-spec"
+version = "0.0.8"
+source = "git+https://github.com/rustsbi/rustsbi?rev=4821073#4821073b56a7223781c11a49aba743785d89d3ea"
+dependencies = [
+ "bitflags",
+]
+
 [[package]]
 name = "sbi-testing"
 version = "0.0.3-alpha.2"
@@ -329,9 +384,20 @@ source = "registry+https://github.com/rust-lang/crates.io-index"
 checksum = "135c0f1ce07ede77a7e1c3daff35d20d37b54fd1037ac02ab9595c231518531e"
 dependencies = [
  "log",
- "riscv",
- "sbi-rt",
- "sbi-spec",
+ "riscv 0.11.1",
+ "sbi-rt 0.0.3 (registry+https://github.com/rust-lang/crates.io-index)",
+ "sbi-spec 0.0.7",
+]
+
+[[package]]
+name = "sbi-testing"
+version = "0.0.3-alpha.2"
+source = "git+https://github.com/rustsbi/rustsbi?rev=4821073#4821073b56a7223781c11a49aba743785d89d3ea"
+dependencies = [
+ "log",
+ "riscv 0.12.1",
+ "sbi-rt 0.0.3 (git+https://github.com/rustsbi/rustsbi?rev=4821073)",
+ "sbi-spec 0.0.8",
 ]
 
 [[package]]
@@ -352,7 +418,7 @@ dependencies = [
 [[package]]
 name = "serde-device-tree"
 version = "0.0.1"
-source = "git+https://github.com/rustsbi/serde-device-tree#6d152e0160ff1dadd2f42638c3d85e0d6a2914bf"
+source = "git+https://github.com/rustsbi/serde-device-tree#cffb488e2bb73f0daae1a889813ef21dc6a02450"
 dependencies = [
  "serde",
 ]
@@ -391,9 +457,9 @@ checksum = "7da8b5736845d9f2fcb837ea5d9e2628564b3b043a70948a3f0b778838c5fb4f"
 
 [[package]]
 name = "syn"
-version = "2.0.89"
+version = "2.0.90"
 source = "registry+https://github.com/rust-lang/crates.io-index"
-checksum = "44d46482f1c1c87acd84dea20c1bf5ebff4c757009ed6bf19cfd36fb10e92c4e"
+checksum = "919d3b74a5dd0ccd15aeb8f93e7006bd9e14c295087c9896a110f490752bcf31"
 dependencies = [
  "proc-macro2",
  "quote",

Cargo.toml

@@ -2,6 +2,7 @@
 resolver = "2"
 members = [
   "prototyper",
+  "bench-kernel",
   "test-kernel",
   "supervisor", 
   "xtask"

bench-kernel/Cargo.toml

@@ -0,0 +1,28 @@
+cargo-features = ["per-package-target"]
+
+[package]
+name = "rustsbi-bench-kernel"
+version = "0.0.0"
+edition.workspace = true
+license.workspace = true
+repository.workspace = true
+forced-target = "riscv64imac-unknown-none-elf"
+publish = false
+
+# See more keys and their definitions at https://doc.rust-lang.org/cargo/reference/manifest.html
+
+[dependencies]
+sbi-testing = { git = "https://github.com/rustsbi/rustsbi", rev = "4821073", features = ["log"] }
+sbi-spec = { git = "https://github.com/rustsbi/rustsbi", rev = "4821073" }
+serde-device-tree = { git = "https://github.com/rustsbi/serde-device-tree", default-features = false }
+serde = { version = "1.0.202", default-features = false, features = ["derive"] }
+log = "0.4"
+riscv = "0.11.1"
+spin = "0.9"
+uart16550 = "0.0.1"
+rcore-console = "0.0.0"
+
+[[bin]]
+name = "rustsbi-bench-kernel"
+test = false
+bench = false

bench-kernel/build.rs

@@ -0,0 +1,52 @@
+use std::{env, path::PathBuf};
+
+fn main() {
+    let out = PathBuf::from(env::var_os("OUT_DIR").unwrap());
+    let ld = &out.join("rustsbi-test-kernel.ld");
+
+    std::fs::write(ld, LINKER_SCRIPT).unwrap();
+
+    println!("cargo:rustc-link-arg=-T{}", ld.display());
+    println!("cargo:rustc-link-search={}", out.display());
+}
+
+const LINKER_SCRIPT: &[u8] = b"OUTPUT_ARCH(riscv)
+ENTRY(_start) 
+SECTIONS {
+    . = 0x80200000;
+    istart = .;
+	  .head.text : ALIGN(8) {		
+        KEEP(*(.head.text))
+	  }
+
+    .text : ALIGN(8) { 
+        *(.text.entry)
+        *(.text .text.*)
+    }
+    .rodata : ALIGN(8) { 
+        srodata = .;
+        *(.rodata .rodata.*)
+        *(.srodata .srodata.*)
+        . = ALIGN(8);  
+        erodata = .;
+    } 
+    .data : ALIGN(8) { 
+        sdata = .;
+        *(.data .data.*)
+        *(.sdata .sdata.*)
+        . = ALIGN(8); 
+        edata = .;
+    }
+    sidata = LOADADDR(.data);
+    .bss (NOLOAD) : ALIGN(8) {  
+        *(.bss.uninit)
+        sbss = .;
+        *(.bss .bss.*)
+        *(.sbss .sbss.*)
+        ebss = .;
+    } 
+    iend = .;
+    /DISCARD/ : {
+        *(.eh_frame)
+    }
+}";

bench-kernel/scripts/rustsbi-bench-kernel.its

@@ -0,0 +1,43 @@
+/*
+ * Configuration to load RustSBI before RustSBI Bench Kernel
+ */
+
+/dts-v1/;
+
+/ {
+			description = "Configuration to load RustSBI before RustSBI Bench Kernel";
+
+			images {
+				kernel {
+					description = "rustsbi-bench-kernel";
+					data = /incbin/("./rustsbi-bench-kernel.bin");
+					type = "standalone";
+					os = "u-boot";
+					arch = "riscv";
+					compression = "none";
+					load = /bits/ 64 <0x80200000>;
+				};
+
+				rustsbi {
+					description = "RustSBI Firmware";
+					data = /incbin/("./rustsbi-prototyper.bin");
+					type = "firmware";
+					os = "opensbi";
+					arch = "riscv";
+					compression = "none";
+					load = /bits/ 64 <0x80100000>;
+					entry = /bits/ 64 <0x80100000>;
+				};
+
+			};
+
+		configurations {
+				default = "conf-1";
+
+				conf-1 {
+					description = "RustSBI & RustSBI Bench Kernel";
+					firmware = "rustsbi";
+					loadables = "kernel";
+				};
+		};
+};

bench-kernel/src/main.rs

@@ -0,0 +1,332 @@
+#![no_std]
+#![no_main]
+#![feature(naked_functions)]
+#![allow(static_mut_refs)]
+
+#[macro_use]
+extern crate rcore_console;
+
+use core::mem::MaybeUninit;
+use core::sync::{atomic::AtomicBool, atomic::AtomicU64, atomic::Ordering};
+use core::{arch::asm, ptr::null};
+use log::*;
+use sbi::SbiRet;
+use sbi_spec::binary::{HartMask, MaskError};
+use sbi_spec::hsm::hart_state;
+use sbi_testing::sbi;
+use serde::Deserialize;
+use serde_device_tree::{
+    buildin::{Node, NodeSeq, Reg, StrSeq},
+    Dtb, DtbPtr,
+};
+use uart16550::Uart16550;
+
+const RISCV_HEAD_FLAGS: u64 = 0;
+const RISCV_HEADER_VERSION: u32 = 0x2;
+const RISCV_IMAGE_MAGIC: u64 = 0x5643534952; /* Magic number, little endian, "RISCV" */
+const RISCV_IMAGE_MAGIC2: u32 = 0x05435352; /* Magic number 2, little endian, "RSC\x05" */
+
+/// boot header
+#[naked]
+#[no_mangle]
+#[link_section = ".head.text"]
+unsafe extern "C" fn _boot_header() -> ! {
+    asm!(
+        "j _start",
+        ".word 0",
+        ".balign 8",
+        ".dword 0x200000",
+        ".dword iend - istart",
+        ".dword {RISCV_HEAD_FLAGS}",
+        ".word  {RISCV_HEADER_VERSION}",
+        ".word  0",
+        ".dword 0",
+        ".dword {RISCV_IMAGE_MAGIC}",
+        ".balign 4",
+        ".word  {RISCV_IMAGE_MAGIC2}",
+        ".word  0",
+        RISCV_HEAD_FLAGS = const RISCV_HEAD_FLAGS,
+        RISCV_HEADER_VERSION = const RISCV_HEADER_VERSION,
+        RISCV_IMAGE_MAGIC = const RISCV_IMAGE_MAGIC,
+        RISCV_IMAGE_MAGIC2 = const RISCV_IMAGE_MAGIC2,
+        options(noreturn)
+    );
+}
+
+const STACK_SIZE: usize = 512 * 1024; // 512 KiB
+const MAX_HART_NUM: usize = 128;
+
+#[allow(dead_code)]
+#[derive(Copy, Clone)]
+struct HartStack([u8; STACK_SIZE]);
+
+impl HartStack {
+    #[inline]
+    pub const fn new() -> Self {
+        HartStack([0; STACK_SIZE])
+    }
+}
+
+#[link_section = ".bss.uninit"]
+static mut STACK: HartStack = HartStack::new();
+#[link_section = ".bss.uninit"]
+static mut HART_STACK: [HartStack; MAX_HART_NUM] = [HartStack::new(); MAX_HART_NUM];
+#[link_section = ".bss.uninit"]
+static mut IPI_SENT: [MaybeUninit<AtomicBool>; MAX_HART_NUM] =
+    [const { MaybeUninit::uninit() }; MAX_HART_NUM];
+#[link_section = ".bss.uninit"]
+static mut SMP_COUNT: usize = 0;
+#[link_section = ".bss.uninit"]
+static mut BOOT_HART_ID: usize = 0;
+
+/// 内核入口。
+///
+/// # Safety
+///
+/// 裸函数。
+#[naked]
+#[no_mangle]
+#[link_section = ".text.entry"]
+unsafe extern "C" fn _start(hartid: usize, device_tree_paddr: usize) -> ! {
+    asm!(
+        // clear bss segment
+        "   la      t0, sbss
+            la      t1, ebss
+        1:  bgeu    t0, t1, 2f
+            sd      zero, 0(t0)
+            addi    t0, t0, 8
+            j       1b",
+        "2:",
+        "   la sp, {stack} + {stack_size}",
+        "   j  {main}",
+        stack_size = const STACK_SIZE,
+        stack      =   sym STACK,
+        main       =   sym rust_main,
+        options(noreturn),
+    )
+}
+
+#[naked]
+#[no_mangle]
+unsafe extern "C" fn init_hart(hartid: usize, opaque: usize) {
+    asm!(
+        "add sp, a1, zero",
+        "csrw sscratch, sp",
+        "call {init_main}",
+        init_main = sym init_main,
+        options(noreturn),
+    )
+}
+
+#[naked]
+#[no_mangle]
+unsafe extern "C" fn core_send_ipi(hartid: usize, opaque: usize) {
+    asm!(
+        "add sp, a1, zero",
+        "csrw sscratch, sp",
+        "call {send_ipi}",
+        send_ipi = sym send_ipi,
+        options(noreturn),
+    )
+}
+
+extern "C" fn send_ipi(hartid: usize) -> ! {
+    if unsafe { !(IPI_SENT[hartid].assume_init_mut().load(Ordering::Relaxed)) } {
+        unsafe {
+            IPI_SENT[hartid]
+                .assume_init_mut()
+                .swap(true, Ordering::AcqRel);
+        };
+        let mut mask = Some(HartMask::from_mask_base(0, 0));
+        for i in 0..unsafe { SMP_COUNT } {
+            if i == unsafe { BOOT_HART_ID } {
+                continue;
+            }
+            if let Some(ref mut mask) = mask {
+                match mask.insert(i) {
+                    Ok(_) => continue,
+                    Err(MaskError::InvalidBit) => {
+                        sbi::remote_sfence_vma(*mask, 0, 0);
+                    }
+                    Err(_) => unreachable!("Failed to construct mask"),
+                }
+            }
+            mask = Some(HartMask::from_mask_base(0b1, i));
+        }
+        if let Some(mask) = mask {
+            sbi::remote_sfence_vma(mask, 0, 0);
+        }
+        unsafe {
+            WAIT_COUNT.fetch_sub(1, Ordering::AcqRel);
+            while WAIT_COUNT.load(Ordering::Relaxed) != 0 {}
+        }
+    } else {
+        unreachable!("resend {}", hartid);
+    }
+    sbi::hart_suspend(sbi::NonRetentive, core_send_ipi as _, unsafe {
+        core::ptr::addr_of!(HART_STACK[hartid + 1]) as _
+    });
+    unreachable!()
+}
+
+extern "C" fn init_main(hartid: usize) -> ! {
+    sbi::hart_suspend(sbi::NonRetentive, core_send_ipi as _, unsafe {
+        core::ptr::addr_of!(HART_STACK[hartid + 1]) as _
+    });
+    unreachable!()
+}
+
+static mut WAIT_COUNT: AtomicU64 = AtomicU64::new(0);
+
+const SUSPENDED: SbiRet = SbiRet::success(hart_state::SUSPENDED);
+
+fn get_time() -> u64 {
+    const CSR_TIME: u32 = 0xc01;
+    let mut low_time: u64;
+    unsafe {
+        asm!("csrr {}, {CSR_TIME}", out(reg) low_time, CSR_TIME = const CSR_TIME);
+    }
+
+    low_time
+}
+
+extern "C" fn rust_main(hartid: usize, dtb_pa: usize) -> ! {
+    #[derive(Deserialize)]
+    struct Tree<'a> {
+        cpus: Cpus<'a>,
+        chosen: Chosen<'a>,
+    }
+    #[derive(Deserialize)]
+    #[serde(rename_all = "kebab-case")]
+    struct Cpus<'a> {
+        timebase_frequency: u32,
+        cpu: NodeSeq<'a>,
+    }
+    #[derive(Deserialize)]
+    #[serde(rename_all = "kebab-case")]
+    struct Chosen<'a> {
+        stdout_path: StrSeq<'a>,
+    }
+    rcore_console::init_console(&Console);
+    rcore_console::set_log_level(option_env!("LOG"));
+    let dtb_ptr = DtbPtr::from_raw(dtb_pa as _).unwrap();
+    let dtb = Dtb::from(dtb_ptr).share();
+    let root: Node = serde_device_tree::from_raw_mut(&dtb).unwrap();
+    let tree: Tree = root.deserialize();
+    let stdout_path = tree.chosen.stdout_path.iter().next().unwrap();
+    if let Some(node) = root.find(stdout_path) {
+        let reg = node.get_prop("reg").unwrap().deserialize::<Reg>();
+        let address = reg.iter().next().unwrap().0.start;
+        unsafe { UART = Uart16550Map(address as _) };
+    }
+    let smp = tree.cpus.cpu.len();
+    let frequency = tree.cpus.timebase_frequency;
+    info!(
+        r"
+ ____                  _       _  __                    _ 
+| __ )  ___ _ __   ___| |__   | |/ /___ _ __ _ __   ___| |
+|  _ \ / _ \ '_ \ / __| '_ \  | ' // _ \ '__| '_ \ / _ \ |
+| |_) |  __/ | | | (__| | | | | . \  __/ |  | | | |  __/ |
+|____/ \___|_| |_|\___|_| |_| |_|\_\___|_|  |_| |_|\___|_|
+==========================================================
+| boot hart id          | {hartid:20} |
+| smp                   | {smp:20} |
+| timebase frequency    | {frequency:17} Hz |
+| dtb physical address  | {dtb_pa:#20x} |
+----------------------------------------------------------"
+    );
+    unsafe {
+        SMP_COUNT = smp;
+        BOOT_HART_ID = hartid;
+    }
+    for i in 0..smp {
+        unsafe {
+            IPI_SENT[i].write(AtomicBool::new(false));
+        }
+        if i != hartid {
+            sbi::hart_start(i, init_hart as _, unsafe {
+                core::ptr::addr_of!(HART_STACK[i + 1]) as _
+            });
+            while sbi::hart_get_status(i) != SUSPENDED {
+                core::hint::spin_loop();
+            }
+        }
+    }
+    info!("Starting test");
+    for i in 0..4 {
+        info!("Test #{i} started");
+        unsafe {
+            for i in 0..smp {
+                IPI_SENT[i].assume_init_mut().swap(false, Ordering::AcqRel);
+                if i != hartid {
+                    while sbi::hart_get_status(i) != SUSPENDED {}
+                }
+            }
+            WAIT_COUNT.swap((smp - 1) as u64, Ordering::AcqRel);
+        }
+        debug!("send ipi!");
+        let start_time = get_time();
+        let mut mask = Some(HartMask::from_mask_base(0, 0));
+        for i in 0..smp {
+            if i == hartid {
+                continue;
+            }
+            if let Some(ref mut mask) = mask {
+                match mask.insert(i) {
+                    Ok(_) => continue,
+                    Err(MaskError::InvalidBit) => {
+                        sbi::send_ipi(*mask);
+                    }
+                    Err(_) => unreachable!("Failed to construct mask"),
+                }
+            }
+            mask = Some(HartMask::from_mask_base(0b1, i));
+        }
+        if let Some(mask) = mask {
+            sbi::send_ipi(mask);
+        }
+        while unsafe { WAIT_COUNT.load(Ordering::Acquire) } != 0 {}
+        let end_time = get_time();
+        println!("Test #{}: {}", i, end_time - start_time);
+    }
+    sbi::system_reset(sbi::Shutdown, sbi::NoReason);
+    unreachable!()
+}
+
+#[cfg_attr(not(test), panic_handler)]
+fn panic(info: &core::panic::PanicInfo) -> ! {
+    let (hart_id, pc): (usize, usize);
+    unsafe { asm!("mv    {}, tp", out(reg) hart_id) };
+    unsafe { asm!("auipc {},  0", out(reg) pc) };
+    info!("[test-kernel-panic] hart {hart_id} {info}");
+    info!("[test-kernel-panic] pc = {pc:#x}");
+    info!("[test-kernel-panic] SBI test FAILED due to panic");
+    sbi::system_reset(sbi::Shutdown, sbi::SystemFailure);
+    loop {}
+}
+
+struct Console;
+static mut UART: Uart16550Map = Uart16550Map(null());
+
+pub struct Uart16550Map(*const Uart16550<u8>);
+
+unsafe impl Sync for Uart16550Map {}
+
+impl Uart16550Map {
+    #[inline]
+    pub fn get(&self) -> &Uart16550<u8> {
+        unsafe { &*self.0 }
+    }
+}
+
+impl rcore_console::Console for Console {
+    #[inline]
+    fn put_char(&self, c: u8) {
+        unsafe { UART.get().write(core::slice::from_ref(&c)) };
+    }
+
+    #[inline]
+    fn put_str(&self, s: &str) {
+        unsafe { UART.get().write(s.as_bytes()) };
+    }
+}

prototyper/Cargo.toml

@@ -33,3 +33,4 @@ bench = false
 [features]
 nemu = []
 payload = []
+fdt = []

prototyper/build.rs

@@ -15,53 +15,65 @@ const LINKER_SCRIPT: &[u8] = b"OUTPUT_ARCH(riscv)
 ENTRY(_start) 
 SECTIONS {
     . = 0x80000000;
+
+    . = ALIGN(0x1000); /* Need this to create proper sections */
+
     sbi_start = .;
-    .text : ALIGN(8) { 
+    .text : ALIGN(0x1000) { 
         *(.text.entry)
         *(.text .text.*)
     }
-    .rodata : ALIGN(8) { 
-        srodata = .;
+
+    .rodata : ALIGN(0x1000) { 
+        sbi_rodata_start = .;
         *(.rodata .rodata.*)
         *(.srodata .srodata.*)
-        . = ALIGN(8);  
+        . = ALIGN(0x1000);  
     } 
+
     .dynsym : ALIGN(8) {
         *(.dynsym)
     }
+
     .rela.dyn : ALIGN(8) {
         __rel_dyn_start = .;
         *(.rela*)
         __rel_dyn_end = .;
     }
 
-    erodata = .;
-    .data : ALIGN(8) { 
-        sdata = .;
+    sbi_rodata_end = .;
+
+	/*
+	 * PMP regions must be to be power-of-2. RX/RW will have separate
+	 * regions, so ensure that the split is power-of-2.
+	 */
+	. = ALIGN(1 << LOG2CEIL((SIZEOF(.rodata) + SIZEOF(.text)
+				+ SIZEOF(.dynsym) + SIZEOF(.rela.dyn))));
+
+    .data : ALIGN(0x1000) { 
+        sbi_data_start = .;
         *(.data .data.*)
         *(.sdata .sdata.*)
-        . = ALIGN(8); 
-        edata = .;
+        . = ALIGN(0x1000); 
+        sbi_data_end = .;
     }
     sidata = LOADADDR(.data);
-    .bss (NOLOAD) : ALIGN(8) {  
+
+    .bss (NOLOAD) : ALIGN(0x1000) {  
         *(.bss.uninit)
-        sbss = .;
+        sbi_bss_start = .;
         *(.bss .bss.*)
         *(.sbss .sbss.*)
-        ebss = .;
+        sbi_bss_end = .;
     } 
     /DISCARD/ : {
         *(.eh_frame)
     }
 
-    . = ALIGN(8);
+	. = ALIGN(0x1000); /* Need this to create proper sections */
     sbi_end = .;
 
-    .text 0x80100000 : ALIGN(8) {
-        *(.fw_fdt)
-    }
-    .text 0x80200000 : ALIGN(8) {
+    .text 0x80200000 : ALIGN(0x1000) {
         *(.payload)
     }
 }";

prototyper/src/board.rs

@@ -1,11 +1,9 @@
 use aclint::SifiveClint;
 use core::{
-    cell::RefCell,
     fmt::{Display, Formatter, Result},
     ops::Range,
     sync::atomic::{AtomicBool, AtomicPtr, Ordering},
 };
-use serde_device_tree::Dtb;
 use sifive_test_device::SifiveTestDevice;
 use spin::Mutex;
 use uart16550::Uart16550;
@@ -23,10 +21,11 @@ use crate::sbi::trap_stack::NUM_HART_MAX;
 use crate::sbi::SBI;
 use crate::{dt, sbi::rfence::SbiRFence};
 
-pub(crate) const UART16650_COMPATIBLE: &str = "ns16550a";
-pub(crate) const UARTAXILITE_COMPATIBLE: &str = "xlnx,xps-uartlite-1.00.a";
-pub(crate) const SIFIVETEST_COMPATIBLE: &str = "sifive,test0";
-pub(crate) const SIFIVECLINT_COMPATIBLE: &str = "riscv,clint0";
+pub(crate) const UART16650U8_COMPATIBLE: [&str; 1] = ["ns16550a"];
+pub(crate) const UART16650U32_COMPATIBLE: [&str; 1] = ["snps,dw-apb-uart"];
+pub(crate) const UARTAXILITE_COMPATIBLE: [&str; 1] = ["xlnx,xps-uartlite-1.00.a"];
+pub(crate) const SIFIVETEST_COMPATIBLE: [&str; 1] = ["sifive,test0"];
+pub(crate) const SIFIVECLINT_COMPATIBLE: [&str; 1] = ["riscv,clint0"];
 
 type BaseAddress = usize;
 /// Store finite-length string on the stack.
@@ -82,8 +81,8 @@ impl Board {
         }
     }
 
-    pub fn init(&mut self, dtb: &RefCell<Dtb>) {
-        self.info_init(dtb);
+    pub fn init(&mut self, fdt_address: usize) {
+        self.info_init(fdt_address);
         self.sbi_init();
         logger::Logger::init().unwrap();
         trap_stack::prepare_for_trap();
@@ -91,38 +90,23 @@ impl Board {
     }
 
     pub fn have_console(&self) -> bool {
-        match self.sbi.console {
-            None => false,
-            Some(_) => true,
-        }
+        self.sbi.console.is_some()
     }
 
     pub fn have_reset(&self) -> bool {
-        match self.sbi.reset {
-            None => false,
-            Some(_) => true,
-        }
+        self.sbi.reset.is_some()
     }
 
     pub fn have_ipi(&self) -> bool {
-        match self.sbi.ipi {
-            None => false,
-            Some(_) => true,
-        }
+        self.sbi.ipi.is_some()
     }
 
     pub fn have_hsm(&self) -> bool {
-        match self.sbi.hsm {
-            None => false,
-            Some(_) => true,
-        }
+        self.sbi.hsm.is_some()
     }
 
     pub fn have_rfence(&self) -> bool {
-        match self.sbi.rfence {
-            None => false,
-            Some(_) => true,
-        }
+        self.sbi.rfence.is_some()
     }
 
     pub fn ready(&self) -> bool {
@@ -140,8 +124,10 @@ impl Board {
         info!("Console device: {:x?}", self.info.console);
     }
 
-    fn info_init(&mut self, dtb: &RefCell<Dtb>) {
-        // TODO: should remove `fail:device_tree_deserialize`.
+    fn info_init(&mut self, fdt_address: usize) {
+        let dtb = dt::parse_device_tree(fdt_address).unwrap_or_else(fail::device_tree_format);
+        let dtb = dtb.share();
+
         let root: serde_device_tree::buildin::Node = serde_device_tree::from_raw_mut(&dtb)
             .unwrap_or_else(fail::device_tree_deserialize_root);
         let tree: dt::Tree = root.deserialize();
@@ -153,11 +139,16 @@ impl Board {
                 let result = info.is_some_and(|info| {
                     let (compatible, regs) = info;
                     for device_id in compatible.iter() {
-                        if device_id == UART16650_COMPATIBLE {
-                            self.info.console = Some((regs.start, MachineConsoleType::Uart16550));
+                        if UART16650U8_COMPATIBLE.contains(&device_id) {
+                            self.info.console = Some((regs.start, MachineConsoleType::Uart16550U8));
+                            return true;
+                        }
+                        if UART16650U32_COMPATIBLE.contains(&device_id) {
+                            self.info.console =
+                                Some((regs.start, MachineConsoleType::Uart16550U32));
                             return true;
                         }
-                        if device_id == UARTAXILITE_COMPATIBLE {
+                        if UARTAXILITE_COMPATIBLE.contains(&device_id) {
                             self.info.console = Some((regs.start, MachineConsoleType::UartAxiLite));
                             return true;
                         }
@@ -178,11 +169,11 @@ impl Board {
                 let base_address = regs.start;
                 for device_id in compatible.iter() {
                     // Initialize clint device.
-                    if device_id == SIFIVECLINT_COMPATIBLE {
+                    if SIFIVECLINT_COMPATIBLE.contains(&device_id) {
                         self.info.ipi = Some(base_address);
                     }
                     // Initialize reset device.
-                    if device_id == SIFIVETEST_COMPATIBLE {
+                    if SIFIVETEST_COMPATIBLE.contains(&device_id) {
                         self.info.reset = Some(base_address);
                     }
                 }
@@ -241,7 +232,8 @@ impl Board {
     fn sbi_console_init(&mut self) {
         if let Some((base, console_type)) = self.info.console {
             let new_console = match console_type {
-                MachineConsoleType::Uart16550 => MachineConsole::Uart16550(base as _),
+                MachineConsoleType::Uart16550U8 => MachineConsole::Uart16550U8(base as _),
+                MachineConsoleType::Uart16550U32 => MachineConsole::Uart16550U32(base as _),
                 MachineConsoleType::UartAxiLite => {
                     MachineConsole::UartAxiLite(MmioUartAxiLite::new(base))
                 }
@@ -273,7 +265,7 @@ impl Board {
 
     fn sbi_hsm_init(&mut self) {
         // TODO: Can HSM work properly when there is no ipi device?
-        if let Some(_) = self.info.ipi {
+        if self.info.ipi.is_some() {
             self.sbi.hsm = Some(SbiHsm);
         } else {
             self.sbi.hsm = None;
@@ -282,7 +274,7 @@ impl Board {
 
     fn sbi_rfence_init(&mut self) {
         // TODO: Can rfence work properly when there is no ipi device?
-        if let Some(_) = self.info.ipi {
+        if self.info.ipi.is_some() {
             self.sbi.rfence = Some(SbiRFence);
         } else {
             self.sbi.rfence = None;
@@ -297,13 +289,15 @@ pub(crate) static mut BOARD: Board = Board::new();
 #[allow(unused)]
 #[derive(Clone, Copy, Debug)]
 pub enum MachineConsoleType {
-    Uart16550,
+    Uart16550U8,
+    Uart16550U32,
     UartAxiLite,
 }
 #[doc(hidden)]
 #[allow(unused)]
 pub enum MachineConsole {
-    Uart16550(*const Uart16550<u8>),
+    Uart16550U8(*const Uart16550<u8>),
+    Uart16550U32(*const Uart16550<u32>),
     UartAxiLite(MmioUartAxiLite),
 }
 
@@ -313,14 +307,16 @@ unsafe impl Sync for MachineConsole {}
 impl ConsoleDevice for MachineConsole {
     fn read(&self, buf: &mut [u8]) -> usize {
         match self {
-            Self::Uart16550(uart16550) => unsafe { (**uart16550).read(buf) },
+            Self::Uart16550U8(uart16550) => unsafe { (**uart16550).read(buf) },
+            Self::Uart16550U32(uart16550) => unsafe { (**uart16550).read(buf) },
             Self::UartAxiLite(axilite) => axilite.read(buf),
         }
     }
 
     fn write(&self, buf: &[u8]) -> usize {
         match self {
-            MachineConsole::Uart16550(uart16550) => unsafe { (**uart16550).write(buf) },
+            MachineConsole::Uart16550U8(uart16550) => unsafe { (**uart16550).write(buf) },
+            MachineConsole::Uart16550U32(uart16550) => unsafe { (**uart16550).write(buf) },
             Self::UartAxiLite(axilite) => axilite.write(buf),
         }
     }

prototyper/src/dt.rs

@@ -40,6 +40,8 @@ pub struct Cpus<'a> {
 pub struct Cpu<'a> {
     /// RISC-V ISA extensions supported by this CPU.
     #[serde(rename = "riscv,isa-extensions")]
+    pub isa_extensions: Option<StrSeq<'a>>,
+    #[serde(rename = "riscv,isa")]
     pub isa: Option<StrSeq<'a>>,
     /// CPU register information.
     pub reg: Reg<'a>,

prototyper/src/fail.rs

@@ -4,7 +4,7 @@ use crate::dt;
 use crate::sbi::reset;
 
 #[cfg(not(feature = "payload"))]
-use crate::platform::dynamic;
+use crate::firmware::dynamic;
 #[cfg(not(feature = "payload"))]
 use riscv::register::mstatus;
 

prototyper/src/platform/dynamic.rs → prototyper/src/firmware/dynamic.rs

@@ -3,33 +3,28 @@
 use core::ops::Range;
 use core::sync::atomic::{AtomicBool, Ordering};
 
-use super::{BootHart, BootInfo};
+use super::BootInfo;
 use crate::fail;
 use crate::riscv_spec::current_hartid;
 
 use riscv::register::mstatus;
 
-/// Gets boot hart information based on opaque and nonstandard_a2 parameters.
+/// Determine whether the current hart is boot hart.
 ///
-/// Returns a BootHart struct containing FDT address and whether this is the boot hart.
-pub fn get_boot_hart(opaque: usize, nonstandard_a2: usize) -> BootHart {
+/// Return true if the current hart is boot hart.
+pub fn is_boot_hart(nonstandard_a2: usize) -> bool {
     // Track whether this is the first hart to boot
     static GENESIS: AtomicBool = AtomicBool::new(true);
 
     let info = read_paddr(nonstandard_a2).unwrap_or_else(fail::use_lottery);
 
     // Determine if this is the boot hart based on hart ID
-    let is_boot_hart = if info.boot_hart == usize::MAX {
+    if info.boot_hart == usize::MAX {
         // If boot_hart is MAX, use atomic bool to determine first hart
         GENESIS.swap(false, Ordering::AcqRel)
     } else {
         // Otherwise check if current hart matches designated boot hart
         current_hartid() == info.boot_hart
-    };
-
-    BootHart {
-        fdt_address: opaque,
-        is_boot_hart,
     }
 }
 
@@ -69,7 +64,7 @@ pub struct DynamicInfo {
 const DYNAMIC_INFO_INVALID_ADDRESSES: usize = 0x00000000;
 const NEXT_ADDR_VALID_ADDRESSES: Range<usize> = 0x80000000..0x90000000;
 pub(crate) const MAGIC: usize = 0x4942534f;
-const SUPPORTED_VERSION: Range<usize> = 2..3;
+const SUPPORTED_VERSION: Range<usize> = 0..3;
 
 /// Error type for dynamic info read failures.
 pub struct DynamicReadError {

prototyper/src/firmware/mod.rs

@@ -0,0 +1,97 @@
+#[cfg(not(feature = "payload"))]
+pub mod dynamic;
+#[cfg(feature = "payload")]
+pub mod payload;
+
+use core::arch::asm;
+use core::ops::Range;
+use riscv::register::mstatus;
+
+pub struct BootInfo {
+    pub next_address: usize,
+    pub mpp: mstatus::MPP,
+}
+
+pub struct BootHart {
+    pub fdt_address: usize,
+    pub is_boot_hart: bool,
+}
+
+#[naked]
+#[link_section = ".rodata.fdt"]
+#[repr(align(16))]
+#[cfg(feature = "fdt")]
+pub unsafe extern "C" fn raw_fdt() {
+    asm!(
+        concat!(".incbin \"", env!("PROTOTYPER_FDT_PATH"), "\""),
+        options(noreturn)
+    );
+}
+
+#[inline]
+#[cfg(feature = "fdt")]
+fn get_fdt_address() -> usize {
+    raw_fdt as usize
+}
+
+#[cfg(not(feature = "payload"))]
+pub use dynamic::{get_boot_info, is_boot_hart};
+#[cfg(feature = "payload")]
+pub use payload::{get_boot_info, is_boot_hart};
+
+/// Gets boot hart information based on opaque and nonstandard_a2 parameters.
+///
+/// Returns a BootHart struct containing FDT address and whether this is the boot hart.
+#[allow(unused_mut, unused_assignments)]
+pub fn get_boot_hart(opaque: usize, nonstandard_a2: usize) -> BootHart {
+    let is_boot_hart = is_boot_hart(nonstandard_a2);
+
+    let mut fdt_address = opaque;
+
+    #[cfg(feature = "fdt")]
+    {
+        fdt_address = get_fdt_address();
+    }
+
+    BootHart {
+        fdt_address,
+        is_boot_hart,
+    }
+}
+
+pub fn set_pmp(memory_range: &Range<usize>) {
+    unsafe {
+        // [0..memory_range.start] RW
+        // [memory_range.start..sbi_start] RWX
+        // [sbi_start..sbi_rodata_start] NONE
+        // [sbi_rodata_start..sbi_rodata_end] NONE
+        // [sbi_rodata_end..sbi_end] NONE
+        // [sbi_end..memory_range.end] RWX
+        // [memory_range.end..INF] RW
+        use riscv::register::*;
+        let mut sbi_start_address: usize;
+        let mut sbi_end_address: usize;
+        let mut rodata_start_address: usize;
+        let mut rodata_end_address: usize;
+        asm!("la {}, sbi_start", out(reg) sbi_start_address, options(nomem));
+        asm!("la {}, sbi_end", out(reg) sbi_end_address, options(nomem));
+        asm!("la {}, sbi_rodata_start", out(reg) rodata_start_address, options(nomem));
+        asm!("la {}, sbi_rodata_end", out(reg) rodata_end_address, options(nomem));
+        pmpcfg0::set_pmp(0, Range::OFF, Permission::NONE, false);
+        pmpaddr0::write(0);
+        pmpcfg0::set_pmp(1, Range::TOR, Permission::RW, false);
+        pmpaddr1::write(memory_range.start >> 2);
+        pmpcfg0::set_pmp(2, Range::TOR, Permission::RWX, false);
+        pmpaddr2::write(sbi_start_address >> 2);
+        pmpcfg0::set_pmp(3, Range::TOR, Permission::NONE, false);
+        pmpaddr3::write(rodata_start_address >> 2);
+        pmpcfg0::set_pmp(4, Range::TOR, Permission::RW, false);
+        pmpaddr4::write(rodata_end_address >> 2);
+        pmpcfg0::set_pmp(5, Range::TOR, Permission::NONE, false);
+        pmpaddr5::write(sbi_end_address >> 2);
+        pmpcfg0::set_pmp(6, Range::TOR, Permission::RWX, false);
+        pmpaddr6::write(memory_range.end >> 2);
+        pmpcfg0::set_pmp(7, Range::TOR, Permission::RW, false);
+        pmpaddr7::write(usize::MAX >> 2);
+    }
+}

prototyper/src/platform/payload.rs → prototyper/src/firmware/payload.rs

@@ -4,13 +4,13 @@ use riscv::register::mstatus;
 
 use super::{BootHart, BootInfo};
 
-pub fn get_boot_hart(_opaque: usize, _nonstandard_a2: usize) -> BootHart {
+/// Determine whether the current hart is boot hart.
+///
+/// Return true if the current hart is boot hart.
+pub fn is_boot_hart(_nonstandard_a2: usize) -> bool {
     static GENESIS: AtomicBool = AtomicBool::new(true);
-    let is_boot_hart = GENESIS.swap(false, Ordering::AcqRel);
-    BootHart {
-        fdt_address: get_fdt_address(),
-        is_boot_hart,
-    }
+    GENESIS.swap(false, Ordering::AcqRel)
+
 }
 
 pub fn get_boot_info(_nonstandard_a2: usize) -> BootInfo {
@@ -20,15 +20,6 @@ pub fn get_boot_info(_nonstandard_a2: usize) -> BootInfo {
     }
 }
 
-#[naked]
-#[link_section = ".fw_fdt"]
-pub unsafe extern "C" fn raw_fdt() {
-    asm!(
-        concat!(".incbin \"", env!("PROTOTYPER_FDT_PATH"), "\""),
-        options(noreturn)
-    );
-}
-
 #[naked]
 #[link_section = ".payload"]
 pub unsafe extern "C" fn payload_image() {
@@ -38,11 +29,6 @@ pub unsafe extern "C" fn payload_image() {
     );
 }
 
-#[inline]
-fn get_fdt_address() -> usize {
-    raw_fdt as usize
-}
-
 #[inline]
 fn get_image_address() -> usize {
     payload_image as usize

prototyper/src/macros.rs

@@ -24,3 +24,28 @@ macro_rules! println {
         }
     }}
 }
+
+#[allow(unused)]
+macro_rules! has_csr {
+    ($($x: expr)*) => {{
+            use core::arch::asm;
+            use riscv::register::mtvec;
+            use crate::sbi::early_trap::expected_trap;
+            let res: usize;
+            unsafe {
+                // Backup old mtvec
+                let mtvec = mtvec::read().bits();
+                // Write expected_trap
+                mtvec::write(expected_trap as _, mtvec::TrapMode::Direct);
+                asm!("addi a0, zero, 0",
+                    "addi a1, zero, 0",
+                    "csrr a2, {}",
+                    "mv {}, a0",
+                    const $($x)*,
+                    out(reg) res,
+                    options(nomem));
+                asm!("csrw mtvec, {}", in(reg) mtvec);
+            }
+            res == 0
+    }};
+}

prototyper/src/main.rs

@@ -1,4 +1,5 @@
 #![feature(naked_functions)]
+#![feature(fn_align)]
 #![no_std]
 #![no_main]
 #![allow(static_mut_refs)]
@@ -11,7 +12,7 @@ mod macros;
 mod board;
 mod dt;
 mod fail;
-mod platform;
+mod firmware;
 mod riscv_spec;
 mod sbi;
 
@@ -19,7 +20,10 @@ use core::arch::asm;
 
 use crate::board::BOARD;
 use crate::riscv_spec::{current_hartid, menvcfg};
-use crate::sbi::extensions::{hart_extension_probe, Extension};
+use crate::sbi::extensions::{
+    hart_extension_probe, hart_privileged_version, privileged_version_detection, Extension,
+    PrivilegedVersion,
+};
 use crate::sbi::hart_context::NextStage;
 use crate::sbi::hsm::local_remote_hsm;
 use crate::sbi::ipi;
@@ -33,29 +37,27 @@ pub const R_RISCV_RELATIVE: usize = 3;
 extern "C" fn rust_main(_hart_id: usize, opaque: usize, nonstandard_a2: usize) {
     // Track whether SBI is initialized and ready.
 
-    let boot_hart_info = platform::get_boot_hart(opaque, nonstandard_a2);
+    let boot_hart_info = firmware::get_boot_hart(opaque, nonstandard_a2);
     // boot hart task entry.
     if boot_hart_info.is_boot_hart {
         // parse the device tree
-        let fdt_addr = boot_hart_info.fdt_address;
-        let dtb = dt::parse_device_tree(fdt_addr).unwrap_or_else(fail::device_tree_format);
-        let dtb = dtb.share();
+        let fdt_address = boot_hart_info.fdt_address;
 
         unsafe {
-            BOARD.init(&dtb);
+            BOARD.init(fdt_address);
             BOARD.print_board_info();
         }
-        platform::set_pmp(unsafe { BOARD.info.memory_range.as_ref().unwrap() });
+        firmware::set_pmp(unsafe { BOARD.info.memory_range.as_ref().unwrap() });
 
         // Get boot information and prepare for kernel entry.
-        let boot_info = platform::get_boot_info(nonstandard_a2);
+        let boot_info = firmware::get_boot_info(nonstandard_a2);
         let (mpp, next_addr) = (boot_info.mpp, boot_info.next_address);
 
         // Start kernel.
         local_remote_hsm().start(NextStage {
             start_addr: next_addr,
             next_mode: mpp,
-            opaque: fdt_addr,
+            opaque: fdt_address,
         });
 
         info!(
@@ -73,9 +75,11 @@ extern "C" fn rust_main(_hart_id: usize, opaque: usize, nonstandard_a2: usize) {
             core::hint::spin_loop()
         }
 
-        platform::set_pmp(unsafe { BOARD.info.memory_range.as_ref().unwrap() });
+        firmware::set_pmp(unsafe { BOARD.info.memory_range.as_ref().unwrap() });
     }
 
+    // Detection Priv Ver
+    privileged_version_detection();
     // Clear all pending IPIs.
     ipi::clear_all();
 
@@ -89,13 +93,15 @@ extern "C" fn rust_main(_hart_id: usize, opaque: usize, nonstandard_a2: usize) {
         // Keep supervisor environment calls and illegal instructions in M-mode.
         medeleg::clear_supervisor_env_call();
         medeleg::clear_illegal_instruction();
-        // Configure environment features based on available extensions.
-        if hart_extension_probe(current_hartid(), Extension::Sstc) {
-            menvcfg::set_bits(
-                menvcfg::STCE | menvcfg::CBIE_INVALIDATE | menvcfg::CBCFE | menvcfg::CBZE,
-            );
-        } else {
-            menvcfg::set_bits(menvcfg::CBIE_INVALIDATE | menvcfg::CBCFE | menvcfg::CBZE);
+        if hart_privileged_version(current_hartid()) >= PrivilegedVersion::Version1_12 {
+            // Configure environment features based on available extensions.
+            if hart_extension_probe(current_hartid(), Extension::Sstc) {
+                menvcfg::set_bits(
+                    menvcfg::STCE | menvcfg::CBIE_INVALIDATE | menvcfg::CBCFE | menvcfg::CBZE,
+                );
+            } else {
+                menvcfg::set_bits(menvcfg::CBIE_INVALIDATE | menvcfg::CBCFE | menvcfg::CBZE);
+            }
         }
         // Set up vectored trap handling.
         mtvec::write(trap_vec as _, mtvec::TrapMode::Vectored);
@@ -116,8 +122,8 @@ unsafe extern "C" fn start() -> ! {
         "   call    {relocation_update}",
         "1:",
         // 3. Hart 0 clear bss segment.
-        "   lla     t0, sbss
-            lla     t1, ebss
+        "   lla     t0, sbi_bss_start
+            lla     t1, sbi_bss_end
          2: bgeu    t0, t1, 3f
             sd      zero, 0(t0)
             addi    t0, t0, 8

prototyper/src/platform/mod.rs

@@ -1,50 +0,0 @@
-#[cfg(not(feature = "payload"))]
-pub mod dynamic;
-#[cfg(feature = "payload")]
-pub mod payload;
-
-use core::arch::asm;
-use core::ops::Range;
-use riscv::register::mstatus;
-
-pub struct BootInfo {
-    pub next_address: usize,
-    pub mpp: mstatus::MPP,
-}
-
-pub struct BootHart {
-    pub fdt_address: usize,
-    pub is_boot_hart: bool,
-}
-
-#[cfg(not(feature = "payload"))]
-pub use dynamic::{get_boot_hart, get_boot_info};
-#[cfg(feature = "payload")]
-pub use payload::{get_boot_hart, get_boot_info};
-
-pub fn set_pmp(memory_range: &Range<usize>) {
-    unsafe {
-        // [0..memory_range.start] RW
-        // [memory_range.start..sbi_start] RWX
-        // [sbi_start..sbi_end] NONE
-        // [sbi_end..memory_range.end] RWX
-        // [memory_range.end..INF] RW
-        use riscv::register::*;
-        let mut sbi_start_address: usize;
-        let mut sbi_end_address: usize;
-        asm!("la {}, sbi_start", out(reg) sbi_start_address, options(nomem));
-        asm!("la {}, sbi_end", out(reg) sbi_end_address, options(nomem));
-        pmpcfg0::set_pmp(0, Range::OFF, Permission::NONE, false);
-        pmpaddr0::write(0);
-        pmpcfg0::set_pmp(1, Range::TOR, Permission::RW, false);
-        pmpaddr1::write(memory_range.start >> 2);
-        pmpcfg0::set_pmp(2, Range::TOR, Permission::RWX, false);
-        pmpaddr2::write(sbi_start_address >> 2);
-        pmpcfg0::set_pmp(3, Range::TOR, Permission::NONE, false);
-        pmpaddr3::write(sbi_end_address >> 2);
-        pmpcfg0::set_pmp(4, Range::TOR, Permission::RWX, false);
-        pmpaddr4::write(memory_range.end >> 2);
-        pmpcfg0::set_pmp(5, Range::TOR, Permission::RW, false);
-        pmpaddr5::write(usize::MAX >> 2);
-    }
-}

prototyper/src/sbi/early_trap.rs

@@ -0,0 +1,20 @@
+use core::arch::asm;
+
+/// When you expected some insts will cause trap, use this.
+/// If trap happened, a0 will set to 1, otherwise will be 0.
+///
+/// This function will change a0 and a1 and will NOT change them back.
+#[naked]
+#[repr(align(16))]
+pub(crate) unsafe extern "C" fn expected_trap() {
+    asm!(
+        "add a0, zero, zero",
+        "add a1, zero, zero",
+        "csrr a1, mepc",
+        "addi a1, a1, 4",
+        "csrw mepc, a1",
+        "addi a0, zero, 1",
+        "mret",
+        options(noreturn)
+    )
+}

prototyper/src/sbi/extensions.rs

@@ -1,13 +1,26 @@
 use serde_device_tree::buildin::NodeSeq;
 
+use crate::riscv_spec::current_hartid;
 use crate::sbi::trap_stack::ROOT_STACK;
-pub struct HartExtensions([bool; Extension::COUNT]);
+
+pub struct HartFeatures {
+    extension: [bool; Extension::COUNT],
+    privileged_version: PrivilegedVersion,
+}
 
 #[derive(Copy, Clone)]
 pub enum Extension {
     Sstc = 0,
 }
 
+#[derive(Copy, Clone, PartialEq, Eq, PartialOrd, Ord)]
+pub enum PrivilegedVersion {
+    Unknown = 0,
+    Version1_10 = 1,
+    Version1_11 = 2,
+    Version1_12 = 3,
+}
+
 impl Extension {
     const COUNT: usize = 1;
     const ITER: [Self; Extension::COUNT] = [Extension::Sstc];
@@ -28,7 +41,16 @@ pub fn hart_extension_probe(hart_id: usize, ext: Extension) -> bool {
     unsafe {
         ROOT_STACK
             .get_mut(hart_id)
-            .map(|x| x.hart_context().extensions.0[ext.index()])
+            .map(|x| x.hart_context().features.extension[ext.index()])
+            .unwrap()
+    }
+}
+
+pub fn hart_privileged_version(hart_id: usize) -> PrivilegedVersion {
+    unsafe {
+        ROOT_STACK
+            .get_mut(hart_id)
+            .map(|x| x.hart_context().features.privileged_version)
             .unwrap()
     }
 }
@@ -40,19 +62,51 @@ pub fn init(cpus: &NodeSeq) {
         let cpu = cpu_iter.deserialize::<Cpu>();
         let hart_id = cpu.reg.iter().next().unwrap().0.start;
         let mut hart_exts = [false; Extension::COUNT];
-        let isa = cpu.isa.unwrap();
-        Extension::ITER.iter().for_each(|ext| {
-            hart_exts[ext.index()] = isa.iter().any(|e| e == ext.as_str());
-        });
+        if cpu.isa_extensions.is_some() {
+            let isa = cpu.isa_extensions.unwrap();
+            Extension::ITER.iter().for_each(|ext| {
+                hart_exts[ext.index()] = isa.iter().any(|e| e == ext.as_str());
+            });
+        } else if cpu.isa.is_some() {
+            let isa_iter = cpu.isa.unwrap();
+            let isa = isa_iter.iter().next().unwrap_or_default();
+            Extension::ITER.iter().for_each(|ext| {
+                hart_exts[ext.index()] = isa.find(ext.as_str()).is_some();
+            })
+        }
 
         unsafe {
             ROOT_STACK
                 .get_mut(hart_id)
-                .map(|stack| stack.hart_context().extensions = HartExtensions(hart_exts))
+                .map(|stack| stack.hart_context().features.extension = hart_exts)
                 .unwrap()
         }
     }
 }
+pub fn privileged_version_detection() {
+    let mut current_priv_ver = PrivilegedVersion::Unknown;
+    {
+        const CSR_MCOUNTEREN: u64 = 0x306;
+        const CSR_MCOUNTINHIBIT: u64 = 0x320;
+        const CSR_MENVCFG: u64 = 0x30a;
+
+        if has_csr!(CSR_MCOUNTEREN) {
+            current_priv_ver = PrivilegedVersion::Version1_10;
+            if has_csr!(CSR_MCOUNTINHIBIT) {
+                current_priv_ver = PrivilegedVersion::Version1_11;
+                if has_csr!(CSR_MENVCFG) {
+                    current_priv_ver = PrivilegedVersion::Version1_12;
+                }
+            }
+        }
+    }
+    unsafe {
+        ROOT_STACK
+            .get_mut(current_hartid())
+            .map(|stack| stack.hart_context().features.privileged_version = current_priv_ver)
+            .unwrap()
+    }
+}
 
 #[cfg(feature = "nemu")]
 pub fn init(cpus: &NodeSeq) {
@@ -62,7 +116,7 @@ pub fn init(cpus: &NodeSeq) {
         unsafe {
             ROOT_STACK
                 .get_mut(hart_id)
-                .map(|stack| stack.hart_context().extensions = HartExtensions(hart_exts))
+                .map(|stack| stack.hart_context().extensions = HartFeatures(hart_exts))
                 .unwrap()
         }
     }

prototyper/src/sbi/hart_context.rs

@@ -1,4 +1,4 @@
-use crate::sbi::extensions::HartExtensions;
+use crate::sbi::extensions::HartFeatures;
 use crate::sbi::hsm::HsmCell;
 use crate::sbi::rfence::RFenceCell;
 use core::ptr::NonNull;
@@ -16,8 +16,8 @@ pub(crate) struct HartContext {
     pub rfence: RFenceCell,
     /// Type of inter-processor interrupt pending.
     pub ipi_type: AtomicU8,
-    /// Supported hart extensions.
-    pub extensions: HartExtensions,
+    /// Supported hart features.
+    pub features: HartFeatures,
 }
 
 impl HartContext {

prototyper/src/sbi/ipi.rs

@@ -79,7 +79,7 @@ impl<T: IpiDevice> rustsbi::Ipi for SbiIpi<T> {
             // There are 2 situation to return invalid_param:
             // 1. We can not get hsm, which usually means this hart_id is bigger than MAX_HART_ID.
             // 2. BOARD hasn't init or this hart_id is not enabled by device tree.
-            // In the next loop, we'll assume that all of above situation will not happend and
+            // In the next loop, we'll assume that all of above situation will not happened and
             // directly send ipi.
             let Some(hsm) = remote_hsm(hart_id) else {
                 return SbiRet::invalid_param();
@@ -140,7 +140,7 @@ impl<T: IpiDevice> SbiIpi<T> {
             // There are 2 situation to return invalid_param:
             // 1. We can not get hsm, which usually means this hart_id is bigger than MAX_HART_ID.
             // 2. BOARD hasn't init or this hart_id is not enabled by device tree.
-            // In the next loop, we'll assume that all of above situation will not happend and
+            // In the next loop, we'll assume that all of above situation will not happened and
             // directly send ipi.
             let Some(hsm) = remote_hsm(hart_id) else {
                 return SbiRet::invalid_param();

prototyper/src/sbi/mod.rs

@@ -6,6 +6,7 @@ pub mod ipi;
 pub mod reset;
 pub mod rfence;
 
+pub mod early_trap;
 pub mod extensions;
 pub mod fifo;
 pub mod hart_context;

test-kernel/src/main.rs

@@ -13,7 +13,7 @@ use uart16550::Uart16550;
 const RISCV_HEAD_FLAGS: u64 = 0;
 const RISCV_HEADER_VERSION: u32 = 0x2;
 const RISCV_IMAGE_MAGIC: u64 = 0x5643534952; /* Magic number, little endian, "RISCV" */
-const RISCV_INAGE_MAGIC2: u32 = 0x05435352; /* Magic number 2, little endian, "RSC\x05" */
+const RISCV_IMAGE_MAGIC2: u32 = 0x05435352; /* Magic number 2, little endian, "RSC\x05" */
 
 /// boot header
 #[naked]
@@ -37,7 +37,7 @@ unsafe extern "C" fn _boot_header() -> ! {
         RISCV_HEAD_FLAGS = const RISCV_HEAD_FLAGS,
         RISCV_HEADER_VERSION = const RISCV_HEADER_VERSION,
         RISCV_IMAGE_MAGIC = const RISCV_IMAGE_MAGIC,
-        RISCV_IMAGE_MAGIC2 = const RISCV_INAGE_MAGIC2,
+        RISCV_IMAGE_MAGIC2 = const RISCV_IMAGE_MAGIC2,
         options(noreturn)
     );
 }

xtask/src/bench.rs

@@ -0,0 +1,72 @@
+use std::{
+    env, fs,
+    process::{Command, ExitStatus},
+};
+
+use clap::Args;
+
+use crate::utils::cargo;
+
+#[derive(Debug, Args, Clone)]
+pub struct BenchArg {
+    /// Package Prototyper and Test-Kernel
+    #[clap(long)]
+    pub pack: bool,
+}
+
+#[must_use]
+pub fn run(arg: &BenchArg) -> Option<ExitStatus> {
+    let arch = "riscv64imac-unknown-none-elf";
+    let current_dir = env::current_dir();
+    let target_dir = current_dir
+        .as_ref()
+        .unwrap()
+        .join("target")
+        .join(arch)
+        .join("release");
+
+    cargo::Cargo::new("build")
+        .package("rustsbi-bench-kernel")
+        .target(arch)
+        .release()
+        .status()
+        .ok()?;
+
+    let exit_status = Command::new("rust-objcopy")
+        .args(["-O", "binary"])
+        .arg("--binary-architecture=riscv64")
+        .arg(target_dir.join("rustsbi-bench-kernel"))
+        .arg(target_dir.join("rustsbi-bench-kernel.bin"))
+        .status()
+        .ok()?;
+
+    if arg.pack {
+        match fs::exists(target_dir.join("rustsbi-prototyper.bin")) {
+            Ok(true) => {}
+            Ok(false) => {
+                panic!(" Couldn't open \"rustsbi-prototyper.bin\": No such file or directory. Please compile Prototyper first");
+            }
+            Err(_) => {
+                panic!("Can't check existence of file rustsbi-prototyper.bin, please compile Prototyper first");
+            }
+        }
+        fs::copy(
+            current_dir
+                .as_ref()
+                .unwrap()
+                .join("bench-kernel")
+                .join("scripts")
+                .join("rustsbi-bench-kernel.its"),
+            target_dir.join("rustsbi-bench-kernel.its"),
+        )
+        .ok()?;
+        env::set_current_dir(&target_dir).ok()?;
+        Command::new("mkimage")
+            .args(["-f", "rustsbi-bench-kernel.its"])
+            .arg("rustsbi-bench-kernel.itb")
+            .status()
+            .ok()?;
+        fs::remove_file(env::current_dir().unwrap().join("rustsbi-bench-kernel.its")).ok()?;
+    }
+    Some(exit_status)
+}

xtask/src/main.rs

@@ -1,12 +1,13 @@
-use std::process::ExitCode;
 use clap::{Parser, Subcommand};
+use std::process::ExitCode;
 
 #[macro_use]
 mod utils;
+mod bench;
 mod prototyper;
 mod test;
 
-
+use crate::bench::BenchArg;
 use crate::prototyper::PrototyperArg;
 use crate::test::TestArg;
 
@@ -25,12 +26,14 @@ struct Cli {
 enum Cmd {
     Prototyper(PrototyperArg),
     Test(TestArg),
+    Bench(BenchArg),
 }
 
 fn main() -> ExitCode {
     if let Some(code) = match Cli::parse().cmd {
         Cmd::Prototyper(ref arg) => prototyper::run(arg),
         Cmd::Test(ref arg) => test::run(arg),
+        Cmd::Bench(ref arg) => bench::run(arg),
     } {
         if code.success() {
             return ExitCode::SUCCESS;

xtask/src/prototyper.rs

@@ -51,7 +51,7 @@ pub fn run(arg: &PrototyperArg) -> Option<ExitStatus> {
             env::current_dir()
                 .unwrap()
                 .join("target")
-                .join(arch.to_string())
+                .join(arch)
                 .join("release")
                 .join("rustsbi-prototyper"),
         )
@@ -59,7 +59,7 @@ pub fn run(arg: &PrototyperArg) -> Option<ExitStatus> {
             env::current_dir()
                 .unwrap()
                 .join("target")
-                .join(arch.to_string())
+                .join(arch)
                 .join("release")
                 .join("rustsbi-prototyper.bin"),
         )

xtask/src/test.rs

@@ -22,7 +22,7 @@ pub fn run(arg: &TestArg) -> Option<ExitStatus> {
         .as_ref()
         .unwrap()
         .join("target")
-        .join(arch.to_string())
+        .join(arch)
         .join("release");
 
     cargo::Cargo::new("build")

xtask/src/utils/mod.rs

@@ -1,4 +1,4 @@
-pub mod cargo; 
+pub mod cargo;
 
 #[macro_use]
 pub mod envs;