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+/// This example illustrates how to use non-usize SBI register values on emulators.
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+///
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+/// We take RISC-V RV128I as an example, since as of now (2025 CE) there are almost no common host
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+/// platforms that support 128-bit pointer width. This example shows how to write an emulator whose
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+/// pointer width differs from that of the host platform.
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+///
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+/// The emulator starts in S-mode, allowing the emulated supervisor software to make SBI calls via
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+/// the `ecall` instruction.
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+use XReg::*;
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+use core::ops::ControlFlow;
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+use sbi_spec::binary::SbiRet;
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+
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+/// Represents a simple RV128I hardware thread (hart) emulator.
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+///
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+/// The hart contains:
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+/// - A set of 32 general-purpose registers (each 128-bit wide)
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+/// - A program counter (PC) also 128-bit wide
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+/// - An instruction memory that holds the binary instructions to execute
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+pub struct SimpleRv128IHart {
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+ xregs: [u128; 32],
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+ pc: u128,
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+ inst_memory: InstMemory<0x2000_0000, { 0x4000 / 4 }>,
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+}
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+
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+/// The main function that sets up the instruction memory, runs the emulator, and prints the result.
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+fn main() {
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+ // Create a new instruction memory with all instructions unimplemented (zeroed out)
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+ let mut memory = InstMemory::new_unimp();
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+
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+ // --- Build a simple program in instruction memory ---
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+ // Call SBI probe_extension to probe the BASE extension which always exists
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+ memory.li(0x0, A0, 0x10);
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+ memory.li(0x4, A6, 3);
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+ memory.li(0x8, A7, 0x10);
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+ memory.ecall(0xC);
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+ // Judge if the SBI call result is zero; if non-zero, jump to emulation failed.
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+ memory.beqz(0x10, A1, 0x1C);
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+ // Emulation success, call SBI system_reset to shutdown emulation
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+ memory.li(0x14, A0, 0x0);
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+ memory.li(0x18, A1, 0x0);
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+ memory.li(0x1C, A6, 0x0);
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+ memory.li(0x20, A7, 0x53525354);
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+ memory.ecall(0x28);
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+ // Emulation failed, call SBI system_reset with SYSTEM_FAILURE to shutdown emulation
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+ memory.li(0x2C, A0, 0x0);
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+ memory.li(0x30, A1, 0x1);
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+ memory.li(0x34, A6, 0x0);
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+ memory.li(0x38, A7, 0x53525354);
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+ memory.ecall(0x44);
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+
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+ // --- Initialize the emulator hart ---
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+ let mut hart = SimpleRv128IHart::new(memory);
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+
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+ // Run the emulation loop, executing one instruction at a time.
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+ // The loop breaks when an SBI call requests to shutdown the emulator (returns a special error value).
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+ let emulation_result = loop {
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+ match hart.stepi() {
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+ Ok(()) => {} // Instruction executed normally; continue to the next one.
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+ Err(Exception::SupervisorEcall) => match handle_ecall(&mut hart) {
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+ // If the SBI call indicates a shutdown (with a special error value), break out of the loop.
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+ ControlFlow::Break(value) => break value,
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+ // Otherwise, continue execution.
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+ ControlFlow::Continue(()) => continue,
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+ },
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+ // Any other exception is considered unexpected, so we print an error and terminate.
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+ Err(e) => {
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+ println!("Emulation failed for unexpected exception: {:?}", e);
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+ return;
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+ }
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+ }
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+ };
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+
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+ // Print the final result of the emulation.
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+ println!("Emulation finished. Result: {}", emulation_result);
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+ if emulation_result == 0 {
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+ println!("✓ Test success!");
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+ } else {
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+ println!("✗ Test failed, emulator returns {}", emulation_result);
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+ }
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+}
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+
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+/* -- Implementations of SimpleRv128Platform -- */
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+
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+/// An instruction memory implementation that holds a fixed number of instructions.
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+///
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+/// `BASE` defines the starting memory address, and `N_INSNS` is the number of 32-bit words.
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+pub struct InstMemory<const BASE: usize, const N_INSNS: usize> {
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+ inner: [u32; N_INSNS],
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+}
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+
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+/// Opcode and function constant definitions for a simplified RISC-V subset.
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+const OPCODE_OP_IMM: u32 = 0b001_0011;
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+const OPCODE_LUI: u32 = 0b011_0111;
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+const OPCODE_BRANCH: u32 = 0b110_0011;
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+const FUNCT3_OP_ADD_SUB: u32 = 0b000;
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+const FUNCT3_BRANCH_BEQ: u32 = 0b000;
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+
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+impl<const BASE: usize, const N_INSNS: usize> InstMemory<BASE, N_INSNS> {
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+ /// Creates a new instance of instruction memory with all instructions set to unimplemented (zero).
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+ pub fn new_unimp() -> Self {
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+ Self {
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+ inner: [0; N_INSNS],
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+ }
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+ }
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+
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+ /// Assemble an ADDI instruction and store it at the given memory index.
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+ ///
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+ /// # Parameters
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+ /// - `idx`: The byte offset at which to place the instruction.
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+ /// - `rd`: The destination register.
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+ /// - `rs`: The source register.
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+ /// - `simm12`: The 12-bit signed immediate.
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+ pub fn addi(&mut self, idx: usize, rd: XReg, rs: XReg, simm12: impl Into<Simm12>) {
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+ let funct3 = FUNCT3_OP_ADD_SUB;
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+ let opcode = OPCODE_OP_IMM;
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+ let word = (u32::from(simm12.into().0) << 20)
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+ | ((rs as u32) << 15)
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+ | (funct3 << 12)
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+ | ((rd as u32) << 7)
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+ | opcode;
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+ self.inner[idx / 4] = word;
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+ }
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+
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+ /// Assemble a LUI (Load Upper Immediate) instruction and store it at the given memory index.
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+ ///
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+ /// # Parameters
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+ /// - `idx`: The byte offset at which to place the instruction.
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+ /// - `rd`: The destination register.
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+ /// - `simm20`: The 20-bit immediate value.
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+ pub fn lui(&mut self, idx: usize, rd: XReg, simm20: impl Into<Simm20>) {
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+ let opcode = OPCODE_LUI;
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+ let word = (u32::from(simm20.into().0) << 12) | ((rd as u32) << 7) | opcode;
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+ self.inner[idx / 4] = word;
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+ }
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+
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+ /// Load an immediate value into a register.
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+ ///
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+ /// This function will generate either a single ADDI instruction (if the upper 20 bits are zero)
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+ /// or a LUI followed by an ADDI instruction.
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+ ///
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+ /// # Parameters
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+ /// - `idx`: The byte offset at which to place the instructions.
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+ /// - `rd`: The destination register.
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+ /// - `imm`: The immediate value (32-bit).
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+ pub fn li(&mut self, idx: usize, rd: XReg, imm: u32) {
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+ let simm20 = (imm >> 12) & 0xFFFFF;
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+ let simm12 = imm & 0xFFF;
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+ if simm20 != 0 {
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+ self.lui(idx, rd, simm20);
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+ self.addi(idx + 0x4, rd, rd, simm12);
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+ } else {
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+ self.addi(idx, rd, XReg::Zero, simm12);
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+ }
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+ }
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+
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+ /// Assemble a BEQ (branch if equal) instruction and store it at the given memory index.
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+ ///
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+ /// # Parameters
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+ /// - `idx`: The byte offset at which to place the instruction.
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+ /// - `rs1`: The first source register.
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+ /// - `rs2`: The second source register.
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+ /// - `offset`: The branch offset.
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+ pub fn beq(&mut self, idx: usize, rs1: XReg, rs2: XReg, offset: impl Into<Offset>) {
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+ let opcode = OPCODE_BRANCH;
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+ let funct3 = FUNCT3_BRANCH_BEQ;
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+ // Convert offset into the proper bit segments for the instruction encoding.
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+ let offset_u32 = u32::from_ne_bytes(i32::to_ne_bytes(offset.into().0));
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+ let simm12_12 = (offset_u32 & 0b1_0000_0000_0000) >> 12;
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+ let simm12_11 = (offset_u32 & 0b1000_0000_0000) >> 11;
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+ let simm12_10_5 = (offset_u32 & 0b111_1110_0000) >> 5;
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+ let simm12_4_1 = (offset_u32 & 0b1_1110) >> 1;
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+ let word = simm12_12 << 31
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+ | simm12_10_5 << 25
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+ | ((rs2 as u32) << 20)
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+ | ((rs1 as u32) << 15)
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+ | (funct3 << 12)
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+ | simm12_4_1 << 8
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+ | simm12_11 << 7
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+ | opcode;
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+ self.inner[idx / 4] = word;
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+ }
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+
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+ /// Assemble a BEQZ (branch if equal to zero) instruction.
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+ ///
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+ /// This is a special case of BEQ where the second register is hardwired to zero.
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+ ///
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+ /// # Parameters
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+ /// - `idx`: The byte offset at which to place the instruction.
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+ /// - `rs`: The register to test for zero.
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+ /// - `offset`: The branch offset.
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+ pub fn beqz(&mut self, idx: usize, rs: XReg, offset: impl Into<Offset>) {
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+ self.beq(idx, rs, Zero, offset);
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+ }
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+
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+ /// Assemble an ECALL instruction at the given offset.
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+ ///
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+ /// This instruction triggers a supervisor call exception.
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+ ///
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+ /// # Parameters
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+ /// - `offset`: The byte offset at which to place the ecall instruction.
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+ pub fn ecall(&mut self, offset: usize) {
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+ let word = 0b000000000000_00000_000_00000_1110011;
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+ self.inner[offset / 4] = word;
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+ }
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+
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+ /// Retrieve an instruction word from instruction memory based on the given pointer.
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+ ///
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+ /// Returns `None` if the pointer is not aligned or outside the allocated memory range.
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+ ///
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+ /// # Parameters
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+ /// - `ptr`: The 128-bit address from which to fetch the instruction.
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+ pub fn get(&mut self, ptr: u128) -> Option<u32> {
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+ if ptr % 4 != 0 || ptr >= (BASE + 4 * N_INSNS) as u128 {
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+ return None;
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+ }
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+ Some(self.inner[(ptr as usize - BASE) / 4])
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+ }
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+}
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+
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+impl SimpleRv128IHart {
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+ /// Creates a new RV128I hart emulator with the given instruction memory.
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+ ///
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+ /// The hart is initialized with all registers set to zero and the program counter
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+ /// set to the base address of the instruction memory.
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+ pub fn new(inst_memory: InstMemory<0x2000_0000, { 0x4000 / 4 }>) -> Self {
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+ Self {
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+ xregs: [0; 32],
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+ pc: 0x2000_0000,
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+ inst_memory,
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+ }
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+ }
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+
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+ /// Execute one instruction step.
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+ ///
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+ /// This function fetches the instruction at the current program counter (PC),
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+ /// decodes it, and then executes it. The PC is updated accordingly.
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+ ///
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+ /// # Returns
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+ /// - `Ok(())` if the instruction executed normally.
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+ /// - `Err(Exception::SupervisorEcall)` if an ecall instruction was encountered (SBI call).
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+ /// - `Err(e)` for any other exceptions.
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+ pub fn stepi(&mut self) -> Result<(), Exception> {
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+ let raw_insn = self
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+ .inst_memory
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+ .get(self.pc)
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+ .ok_or(Exception::InstructionAccessFault)?;
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+
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+ println!("Raw insn at 0x{:x?} is 0x{:x?}", self.pc, raw_insn);
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+
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+ // Attempt to decode the raw instruction into one of the supported instruction variants.
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+ let parsed_insn =
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+ Instruction::try_from(raw_insn).map_err(|_| Exception::IllegalInstruction)?;
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+
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+ match parsed_insn {
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+ Instruction::Addi(rd, rs, simm12) => {
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+ self.xregs[rd as usize] = self.xregs[rs as usize] + simm12.0 as u128;
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+ self.pc = self.pc.wrapping_add(4);
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+ }
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+ Instruction::Lui(rd, simm20) => {
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+ self.xregs[rd as usize] = (simm20.0 as u128) << 12;
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+ self.pc = self.pc.wrapping_add(4);
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+ }
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+ Instruction::Beq(rs1, rs2, offset) => {
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+ if self.xregs[rs1 as usize] == self.xregs[rs2 as usize] {
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+ self.pc = self.pc.wrapping_add_signed(offset.0 as i128);
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+ } else {
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+ self.pc = self.pc.wrapping_add(4);
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+ }
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+ }
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+ Instruction::Ecall => return Err(Exception::SupervisorEcall),
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+ }
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+
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+ Ok(())
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+ }
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+}
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+
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+/// RISC-V exceptions that may occur during emulation.
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+#[derive(Debug)]
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+pub enum Exception {
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+ /// The instruction is illegal or not supported.
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+ IllegalInstruction,
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+ /// The instruction memory access failed (e.g., due to an out-of-bound address).
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+ InstructionAccessFault,
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+ /// An ecall was executed in supervisor mode.
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+ SupervisorEcall,
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+}
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+
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+/// Enum representing the supported instructions in our simplified RV128I emulator.
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+#[derive(Debug)]
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+pub enum Instruction {
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+ /// ADDI instruction: rd = rs + immediate.
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+ Addi(XReg, XReg, Simm12),
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+ /// LUI instruction: rd = immediate << 12.
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+ Lui(XReg, Simm20),
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+ /// BEQ instruction: if (rs1 == rs2) branch to PC + offset.
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+ Beq(XReg, XReg, Offset),
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+ /// ECALL instruction to trigger a supervisor call.
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+ Ecall,
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+}
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+
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+impl TryFrom<u32> for Instruction {
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+ type Error = ();
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+
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+ /// Attempts to decode a 32-bit word into a supported Instruction.
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+ ///
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+ /// Returns an error if the instruction encoding does not match any known pattern.
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+ fn try_from(value: u32) -> Result<Self, Self::Error> {
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+ let opcode = value & 0x7F;
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+ let rd = ((value >> 7) & 0x1F).try_into().unwrap();
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+ let rs1 = ((value >> 15) & 0x1F).try_into().unwrap();
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+ let rs2 = ((value >> 20) & 0x1F).try_into().unwrap();
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+ let funct3 = (value >> 12) & 0b111;
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+ let simm12 = (value >> 20).into();
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+ let simm20 = (value >> 12).into();
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+ // Decode the branch offset from its scattered bit fields.
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+ let offset = {
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+ let offset12 = value >> 31;
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+ let offset10_5 = (value >> 25) & 0x3F;
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+ let offset4_1 = (value >> 8) & 0xF;
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+ let offset11 = (value >> 7) & 0x1;
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+ let value = (offset4_1 << 1) | (offset10_5 << 5) | (offset11 << 11) | (offset12 << 12);
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+ value.into()
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+ };
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+ if opcode == OPCODE_OP_IMM && funct3 == FUNCT3_OP_ADD_SUB {
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+ Ok(Self::Addi(rd, rs1, simm12))
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+ } else if opcode == OPCODE_LUI {
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+ Ok(Self::Lui(rd, simm20))
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+ } else if opcode == OPCODE_BRANCH && funct3 == FUNCT3_BRANCH_BEQ {
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+ Ok(Self::Beq(rs1, rs2, offset))
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+ } else if value == 0b000000000000_00000_000_00000_1110011 {
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+ Ok(Self::Ecall)
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+ } else {
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+ Err(())
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+ }
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+ }
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+}
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+
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+/// Enumeration of RISC-V registers.
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+///
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+/// Each variant corresponds to a register name and its associated register number.
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+#[derive(Clone, Copy, Debug)]
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+pub enum XReg {
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+ Zero = 0,
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+ Ra = 1,
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+ Sp = 2,
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+ Gp = 3,
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+ Tp = 4,
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+ T0 = 5,
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+ T1 = 6,
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+ T2 = 7,
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+ S0 = 8,
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+ S1 = 9,
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+ A0 = 10,
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+ A1 = 11,
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+ A2 = 12,
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+ A3 = 13,
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+ A4 = 14,
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+ A5 = 15,
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+ A6 = 16,
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+ A7 = 17,
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+ S2 = 18,
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+ S3 = 19,
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+ S4 = 20,
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+ S5 = 21,
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+ S6 = 22,
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+ S7 = 23,
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+ S8 = 24,
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+ S9 = 25,
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+ S10 = 26,
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+ S11 = 27,
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|
+ T3 = 28,
|
|
|
+ T4 = 29,
|
|
|
+ T5 = 30,
|
|
|
+ T6 = 31,
|
|
|
+}
|
|
|
+
|
|
|
+impl TryFrom<u32> for XReg {
|
|
|
+ type Error = ();
|
|
|
+
|
|
|
+ /// Convert a u32 into an XReg.
|
|
|
+ /// Returns an error if the value does not correspond to a valid register number.
|
|
|
+ fn try_from(value: u32) -> Result<Self, Self::Error> {
|
|
|
+ Ok(match value {
|
|
|
+ 0 => Zero,
|
|
|
+ 1 => Ra,
|
|
|
+ 2 => Sp,
|
|
|
+ 3 => Gp,
|
|
|
+ 4 => Tp,
|
|
|
+ 5 => T0,
|
|
|
+ 6 => T1,
|
|
|
+ 7 => T2,
|
|
|
+ 8 => S0,
|
|
|
+ 9 => S1,
|
|
|
+ 10 => A0,
|
|
|
+ 11 => A1,
|
|
|
+ 12 => A2,
|
|
|
+ 13 => A3,
|
|
|
+ 14 => A4,
|
|
|
+ 15 => A5,
|
|
|
+ 16 => A6,
|
|
|
+ 17 => A7,
|
|
|
+ 18 => S2,
|
|
|
+ 19 => S3,
|
|
|
+ 20 => S4,
|
|
|
+ 21 => S5,
|
|
|
+ 22 => S6,
|
|
|
+ 23 => S7,
|
|
|
+ 24 => S8,
|
|
|
+ 25 => S9,
|
|
|
+ 26 => S10,
|
|
|
+ 27 => S11,
|
|
|
+ 28 => T3,
|
|
|
+ 29 => T4,
|
|
|
+ 30 => T5,
|
|
|
+ 31 => T6,
|
|
|
+ _ => return Err(()),
|
|
|
+ })
|
|
|
+ }
|
|
|
+}
|
|
|
+
|
|
|
+/// A 12-bit signed immediate value used in instructions such as ADDI.
|
|
|
+#[derive(Clone, Copy, Debug)]
|
|
|
+pub struct Simm12(u16);
|
|
|
+
|
|
|
+impl From<u32> for Simm12 {
|
|
|
+ fn from(value: u32) -> Self {
|
|
|
+ Self((value & 0x0FFF) as u16)
|
|
|
+ }
|
|
|
+}
|
|
|
+
|
|
|
+/// A 20-bit immediate value used in instructions such as LUI.
|
|
|
+#[derive(Clone, Copy, Debug)]
|
|
|
+pub struct Simm20(u32);
|
|
|
+
|
|
|
+impl From<u32> for Simm20 {
|
|
|
+ fn from(value: u32) -> Self {
|
|
|
+ Self(value & 0xFFFFF)
|
|
|
+ }
|
|
|
+}
|
|
|
+
|
|
|
+/// A branch offset used in branch instructions.
|
|
|
+#[derive(Clone, Copy, Debug)]
|
|
|
+pub struct Offset(i32);
|
|
|
+
|
|
|
+impl From<i32> for Offset {
|
|
|
+ fn from(value: i32) -> Self {
|
|
|
+ Self(value & 0x1FFE)
|
|
|
+ }
|
|
|
+}
|
|
|
+
|
|
|
+impl From<u32> for Offset {
|
|
|
+ fn from(mut value: u32) -> Self {
|
|
|
+ value = value & 0x1FFE;
|
|
|
+ if value & 0x1000 != 0 {
|
|
|
+ value |= 0xFFFFE000;
|
|
|
+ }
|
|
|
+ let ans = i32::from_ne_bytes(u32::to_ne_bytes(value));
|
|
|
+ Self(ans)
|
|
|
+ }
|
|
|
+}
|
|
|
+
|
|
|
+// A simple SBI implementation without using RustSBI.
|
|
|
+
|
|
|
+/// Handle the supervisor call (ecall) exception by performing an SBI call.
|
|
|
+///
|
|
|
+/// This function extracts the parameters from the hart's registers, performs the SBI call, and
|
|
|
+/// then updates the hart's registers and program counter with the results.
|
|
|
+///
|
|
|
+/// # Parameters
|
|
|
+/// - `hart`: A mutable reference to the RV128I hart emulator.
|
|
|
+///
|
|
|
+/// # Returns
|
|
|
+/// - `ControlFlow::Break(value)` if the SBI call indicates that the platform should shutdown.
|
|
|
+/// - `ControlFlow::Continue(())` if the emulation should continue.
|
|
|
+fn handle_ecall(hart: &mut SimpleRv128IHart) -> ControlFlow<u128> {
|
|
|
+ println!("Handle ecall, registers: {:x?}", hart.xregs);
|
|
|
+ // Extract SBI call parameters from registers A0-A5.
|
|
|
+ let param = [
|
|
|
+ hart.xregs[A0 as usize],
|
|
|
+ hart.xregs[A1 as usize],
|
|
|
+ hart.xregs[A2 as usize],
|
|
|
+ hart.xregs[A3 as usize],
|
|
|
+ hart.xregs[A4 as usize],
|
|
|
+ hart.xregs[A5 as usize],
|
|
|
+ ];
|
|
|
+ // Call the SBI handler with the extension and function numbers from registers A7 and A6.
|
|
|
+ let ret = handle_sbi_call(hart.xregs[A7 as usize], hart.xregs[A6 as usize], param);
|
|
|
+ println!("SbiRet: {:?}", ret);
|
|
|
+ // If the SBI call returns the special error value (0x114514), signal shutdown.
|
|
|
+ if ret.error == 0x114514 {
|
|
|
+ return ControlFlow::Break(ret.value);
|
|
|
+ }
|
|
|
+ // Otherwise, store the error and return values into registers A0 and A1, respectively.
|
|
|
+ hart.xregs[A0 as usize] = ret.error;
|
|
|
+ hart.xregs[A1 as usize] = ret.value;
|
|
|
+ // Advance the program counter past the ecall instruction.
|
|
|
+ hart.pc = hart.pc.wrapping_add(4);
|
|
|
+ ControlFlow::Continue(())
|
|
|
+}
|
|
|
+
|
|
|
+/// Handle an SBI call given the extension and function numbers, along with its parameters.
|
|
|
+///
|
|
|
+/// This is a simple SBI implementation (without using RustSBI) that supports a few functions:
|
|
|
+/// - BASE probe_extension: checks if an SBI extension exists.
|
|
|
+/// - SRST system_reset: performs a system reset (shutdown).
|
|
|
+///
|
|
|
+/// Note that the returned `SbiRet<u128>` represents an `SbiRet` with `u128` as the SBI register
|
|
|
+/// type.
|
|
|
+///
|
|
|
+/// # Parameters
|
|
|
+/// - `extension`: The SBI extension identifier (from register A7).
|
|
|
+/// - `function`: The SBI function number (from register A6).
|
|
|
+/// - `param`: An array containing SBI call parameters (from registers A0-A5).
|
|
|
+///
|
|
|
+/// # Returns
|
|
|
+/// An `SbiRet` structure containing the error and return values.
|
|
|
+fn handle_sbi_call(extension: u128, function: u128, param: [u128; 6]) -> SbiRet<u128> {
|
|
|
+ match (extension, function) {
|
|
|
+ // BASE probe_extension: if the parameter matches the BASE extension identifier, return 1.
|
|
|
+ (0x10, 3) => {
|
|
|
+ if param[0] == 0x10 {
|
|
|
+ SbiRet::success(1)
|
|
|
+ } else {
|
|
|
+ SbiRet::success(0)
|
|
|
+ }
|
|
|
+ }
|
|
|
+ // SRST system_reset: perform a system reset if the reset type is shutdown.
|
|
|
+ (0x53525354, 0) => {
|
|
|
+ let (reset_type, reset_reason) = (param[0], param[1]);
|
|
|
+ if reset_type == sbi_spec::srst::RESET_TYPE_SHUTDOWN as u128 {
|
|
|
+ // Use a special SBI error value (0x114514) to signal platform shutdown.
|
|
|
+ SbiRet {
|
|
|
+ value: reset_reason,
|
|
|
+ error: 0x114514,
|
|
|
+ }
|
|
|
+ } else {
|
|
|
+ SbiRet::not_supported()
|
|
|
+ }
|
|
|
+ }
|
|
|
+ // All other SBI calls are not supported.
|
|
|
+ _ => SbiRet::not_supported(),
|
|
|
+ }
|
|
|
+}
|
Zhouqi Jiang