Small fix

platform/qemu/Cargo.toml

@@ -12,7 +12,7 @@ rustsbi = { path = "../../rustsbi" }
 linked_list_allocator = "0.8"
 lazy_static = { version = "1", features = ["spin_no_std"] }
 spin = "0.5"
-riscv = { version = "0.6", features = ["inline-asm"] }
+riscv = { git = "https://github.com/rust-embedded/riscv", features = ["inline-asm"] }
 
 # 这几个其实不用，应该使用对应的hal库实现
 embedded-hal = "1.0.0-alpha.1"

platform/qemu/src/hal.rs

@@ -12,6 +12,8 @@ pub struct Reset;
 
 impl rustsbi::Reset for Reset {
     fn reset(&self) -> ! {
+        // todo: only exit after all harts finished
+        loop {}
         const VIRT_TEST: *mut u64 = 0x10_0000 as *mut u64;
         // Fail = 0x3333,
         // Pass = 0x5555,

platform/qemu/src/main.rs

@@ -16,7 +16,7 @@ use rustsbi::{println, enter_privileged};
 
 use riscv::register::{
     mcause::{self, Exception, Interrupt, Trap},
-    mepc, mhartid, mideleg, mie, mip,
+    medeleg, mepc, mhartid, mideleg, mie, mip,
     mstatus::{self, MPP},
     mtval,
     mtvec::{self, TrapMode},
@@ -135,6 +135,8 @@ fn main() -> ! {
         mideleg::set_sext();
         mideleg::set_stimer();
         mideleg::set_ssoft();
+        // todo: more medeleg
+        medeleg::set_breakpoint();
         mie::set_mext();
         // 不打开mie::set_mtimer
         mie::set_msoft();