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@@ -0,0 +1,601 @@
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+//! Module for dealing with a PCI bus in general, without anything specific to VirtIO.
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+
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+use bitflags::bitflags;
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+use core::{
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+ convert::TryFrom,
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+ fmt::{self, Display, Formatter},
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+};
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+use log::warn;
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+
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+const INVALID_READ: u32 = 0xffffffff;
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+
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+/// The maximum number of devices on a bus.
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+const MAX_DEVICES: u8 = 32;
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+/// The maximum number of functions on a device.
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+const MAX_FUNCTIONS: u8 = 8;
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+
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+/// The offset in bytes to the status and command fields within PCI configuration space.
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+const STATUS_COMMAND_OFFSET: u8 = 0x04;
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+/// The offset in bytes to BAR0 within PCI configuration space.
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+const BAR0_OFFSET: u8 = 0x10;
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+
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+/// ID for vendor-specific PCI capabilities.
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+pub const PCI_CAP_ID_VNDR: u8 = 0x09;
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+
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+bitflags! {
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+ /// The status register in PCI configuration space.
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+ pub struct Status: u16 {
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+ // Bits 0-2 are reserved.
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+ /// The state of the device's INTx# signal.
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+ const INTERRUPT_STATUS = 1 << 3;
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+ /// The device has a linked list of capabilities.
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+ const CAPABILITIES_LIST = 1 << 4;
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+ /// The device is capabile of running at 66 MHz rather than 33 MHz.
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+ const MHZ_66_CAPABLE = 1 << 5;
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+ // Bit 6 is reserved.
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+ /// The device can accept fast back-to-back transactions not from the same agent.
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+ const FAST_BACK_TO_BACK_CAPABLE = 1 << 7;
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+ /// The bus agent observed a parity error (if parity error handling is enabled).
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+ const MASTER_DATA_PARITY_ERROR = 1 << 8;
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+ // Bits 9-10 are DEVSEL timing.
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+ /// A target device terminated a transaction with target-abort.
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+ const SIGNALED_TARGET_ABORT = 1 << 11;
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+ /// A master device transaction was terminated with target-abort.
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+ const RECEIVED_TARGET_ABORT = 1 << 12;
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+ /// A master device transaction was terminated with master-abort.
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+ const RECEIVED_MASTER_ABORT = 1 << 13;
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+ /// A device asserts SERR#.
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+ const SIGNALED_SYSTEM_ERROR = 1 << 14;
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+ /// The device detects a parity error, even if parity error handling is disabled.
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+ const DETECTED_PARITY_ERROR = 1 << 15;
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+ }
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+}
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+
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+bitflags! {
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+ /// The command register in PCI configuration space.
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+ pub struct Command: u16 {
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+ /// The device can respond to I/O Space accesses.
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+ const IO_SPACE = 1 << 0;
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+ /// The device can respond to Memory Space accesses.
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+ const MEMORY_SPACE = 1 << 1;
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+ /// The device can behave as a bus master.
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+ const BUS_MASTER = 1 << 2;
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+ /// The device can monitor Special Cycle operations.
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+ const SPECIAL_CYCLES = 1 << 3;
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+ /// The device can generate the Memory Write and Invalidate command.
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+ const MEMORY_WRITE_AND_INVALIDATE_ENABLE = 1 << 4;
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+ /// The device will snoop palette register data.
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+ const VGA_PALETTE_SNOOP = 1 << 5;
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+ /// The device should take its normal action when a parity error is detected.
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+ const PARITY_ERROR_RESPONSE = 1 << 6;
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+ // Bit 7 is reserved.
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+ /// The SERR# driver is enabled.
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+ const SERR_ENABLE = 1 << 8;
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+ /// The device is allowed to generate fast back-to-back transactions.
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+ const FAST_BACK_TO_BACK_ENABLE = 1 << 9;
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+ /// Assertion of the device's INTx# signal is disabled.
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+ const INTERRUPT_DISABLE = 1 << 10;
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+ }
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+}
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+
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+/// Errors accessing a PCI device.
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+#[derive(Copy, Clone, Debug, Eq, PartialEq)]
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+pub enum PciError {
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+ /// The device reported an invalid BAR type.
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+ InvalidBarType,
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+}
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+
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+impl Display for PciError {
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+ fn fmt(&self, f: &mut Formatter) -> fmt::Result {
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+ match self {
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+ Self::InvalidBarType => write!(f, "Invalid PCI BAR type."),
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+ }
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+ }
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+}
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+
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+/// The root complex of a PCI bus.
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+#[derive(Debug)]
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+pub struct PciRoot {
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+ mmio_base: *mut u32,
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+ cam: Cam,
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+}
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+
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+/// A PCI Configuration Access Mechanism.
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+#[derive(Copy, Clone, Debug, Eq, PartialEq)]
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+pub enum Cam {
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+ /// The PCI memory-mapped Configuration Access Mechanism.
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+ ///
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+ /// This provides access to 256 bytes of configuration space per device function.
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+ MmioCam,
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+ /// The PCIe memory-mapped Enhanced Configuration Access Mechanism.
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+ ///
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+ /// This provides access to 4 KiB of configuration space per device function.
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+ Ecam,
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+}
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+
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+impl Cam {
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+ /// Returns the total size in bytes of the memory-mapped region.
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+ pub const fn size(self) -> u32 {
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+ match self {
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+ Self::MmioCam => 0x1000000,
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+ Self::Ecam => 0x10000000,
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+ }
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+ }
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+}
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+
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+impl PciRoot {
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+ /// Wraps the PCI root complex with the given MMIO base address.
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+ ///
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+ /// Panics if the base address is not aligned to a 4-byte boundary.
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+ ///
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+ /// # Safety
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+ ///
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+ /// `mmio_base` must be a valid pointer to an appropriately-mapped MMIO region of at least
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+ /// 16 MiB (if `cam == Cam::MmioCam`) or 256 MiB (if `cam == Cam::Ecam`). The pointer must be
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+ /// valid for the entire lifetime of the program (i.e. `'static`), which implies that no Rust
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+ /// references may be used to access any of the memory region at any point.
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+ pub unsafe fn new(mmio_base: *mut u8, cam: Cam) -> Self {
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+ assert!(mmio_base as usize & 0x3 == 0);
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+ Self {
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+ mmio_base: mmio_base as *mut u32,
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+ cam,
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+ }
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+ }
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+
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+ /// Makes a clone of the `PciRoot`, pointing at the same MMIO region.
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+ ///
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+ /// # Safety
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+ ///
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+ /// This function allows concurrent mutable access to the PCI CAM. To avoid this causing
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+ /// problems, the returned `PciRoot` instance must only be used to read read-only fields.
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+ unsafe fn unsafe_clone(&self) -> Self {
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+ Self {
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+ mmio_base: self.mmio_base,
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+ cam: self.cam,
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+ }
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+ }
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+
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+ fn cam_offset(&self, device_function: DeviceFunction, register_offset: u8) -> u32 {
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+ assert!(device_function.valid());
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+
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+ let bdf = (device_function.bus as u32) << 8
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+ | (device_function.device as u32) << 3
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+ | device_function.function as u32;
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+ let address =
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+ bdf << match self.cam {
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+ Cam::MmioCam => 8,
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+ Cam::Ecam => 12,
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+ } | register_offset as u32;
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+ // Ensure that address is within range.
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+ assert!(address < self.cam.size());
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+ // Ensure that address is word-aligned.
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+ assert!(address & 0x3 == 0);
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+ address
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+ }
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+
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+ /// Reads 4 bytes from configuration space using the appropriate CAM.
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+ pub(crate) fn config_read_word(
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+ &self,
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+ device_function: DeviceFunction,
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+ register_offset: u8,
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+ ) -> u32 {
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+ let address = self.cam_offset(device_function, register_offset);
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+ // Safe because both the `mmio_base` and the address offset are properly aligned, and the
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+ // resulting pointer is within the MMIO range of the CAM.
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+ unsafe {
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+ // Right shift to convert from byte offset to word offset.
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+ (self.mmio_base.add((address >> 2) as usize)).read_volatile()
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+ }
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+ }
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+
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+ /// Writes 4 bytes to configuration space using the appropriate CAM.
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+ pub(crate) fn config_write_word(
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+ &mut self,
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+ device_function: DeviceFunction,
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+ register_offset: u8,
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+ data: u32,
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+ ) {
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+ let address = self.cam_offset(device_function, register_offset);
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+ // Safe because both the `mmio_base` and the address offset are properly aligned, and the
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+ // resulting pointer is within the MMIO range of the CAM.
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+ unsafe {
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+ // Right shift to convert from byte offset to word offset.
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+ (self.mmio_base.add((address >> 2) as usize)).write_volatile(data)
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+ }
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+ }
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+
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+ /// Enumerates PCI devices on the given bus.
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+ pub fn enumerate_bus(&self, bus: u8) -> BusDeviceIterator {
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+ // Safe because the BusDeviceIterator only reads read-only fields.
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+ let root = unsafe { self.unsafe_clone() };
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+ BusDeviceIterator {
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+ root,
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+ next: DeviceFunction {
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+ bus,
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+ device: 0,
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+ function: 0,
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+ },
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+ }
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+ }
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+
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+ /// Reads the status and command registers of the given device function.
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+ pub fn get_status_command(&self, device_function: DeviceFunction) -> (Status, Command) {
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+ let status_command = self.config_read_word(device_function, STATUS_COMMAND_OFFSET);
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+ let status = Status::from_bits_truncate((status_command >> 16) as u16);
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+ let command = Command::from_bits_truncate(status_command as u16);
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+ (status, command)
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+ }
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+
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+ /// Sets the command register of the given device function.
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+ pub fn set_command(&mut self, device_function: DeviceFunction, command: Command) {
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+ self.config_write_word(
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+ device_function,
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+ STATUS_COMMAND_OFFSET,
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+ command.bits().into(),
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+ );
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+ }
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+
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+ /// Gets an iterator over the capabilities of the given device function.
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+ pub fn capabilities(&self, device_function: DeviceFunction) -> CapabilityIterator {
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+ CapabilityIterator {
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+ root: self,
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+ device_function,
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+ next_capability_offset: self.capabilities_offset(device_function),
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+ }
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+ }
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+
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+ /// Gets information about the given BAR of the given device function.
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+ pub fn bar_info(
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+ &mut self,
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+ device_function: DeviceFunction,
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+ bar_index: u8,
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+ ) -> Result<BarInfo, PciError> {
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+ let bar_orig = self.config_read_word(device_function, BAR0_OFFSET + 4 * bar_index);
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+
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+ // Get the size of the BAR.
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+ self.config_write_word(device_function, BAR0_OFFSET + 4 * bar_index, 0xffffffff);
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+ let size_mask = self.config_read_word(device_function, BAR0_OFFSET + 4 * bar_index);
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+ // A wrapping add is necessary to correctly handle the case of unused BARs, which read back
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+ // as 0, and should be treated as size 0.
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+ let size = (!(size_mask & 0xfffffff0)).wrapping_add(1);
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+
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+ // Restore the original value.
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+ self.config_write_word(device_function, BAR0_OFFSET + 4 * bar_index, bar_orig);
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+
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+ if bar_orig & 0x00000001 == 0x00000001 {
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+ // I/O space
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+ let address = bar_orig & 0xfffffffc;
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+ Ok(BarInfo::IO { address, size })
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+ } else {
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+ // Memory space
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+ let mut address = u64::from(bar_orig & 0xfffffff0);
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+ let prefetchable = bar_orig & 0x00000008 != 0;
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+ let address_type = MemoryBarType::try_from(((bar_orig & 0x00000006) >> 1) as u8)?;
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+ if address_type == MemoryBarType::Width64 {
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+ if bar_index >= 5 {
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+ return Err(PciError::InvalidBarType);
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+ }
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+ let address_top =
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+ self.config_read_word(device_function, BAR0_OFFSET + 4 * (bar_index + 1));
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+ address |= u64::from(address_top) << 32;
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+ }
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+ Ok(BarInfo::Memory {
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+ address_type,
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+ prefetchable,
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+ address,
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+ size,
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+ })
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+ }
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+ }
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+
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+ /// Sets the address of the given 32-bit memory or I/O BAR of the given device function.
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+ pub fn set_bar_32(&mut self, device_function: DeviceFunction, bar_index: u8, address: u32) {
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+ self.config_write_word(device_function, BAR0_OFFSET + 4 * bar_index, address);
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+ }
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+
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+ /// Sets the address of the given 64-bit memory BAR of the given device function.
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+ pub fn set_bar_64(&mut self, device_function: DeviceFunction, bar_index: u8, address: u64) {
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+ self.config_write_word(device_function, BAR0_OFFSET + 4 * bar_index, address as u32);
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+ self.config_write_word(
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+ device_function,
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+ BAR0_OFFSET + 4 * (bar_index + 1),
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+ (address >> 32) as u32,
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+ );
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+ }
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+
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+ /// Gets the capabilities 'pointer' for the device function, if any.
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+ fn capabilities_offset(&self, device_function: DeviceFunction) -> Option<u8> {
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+ let (status, _) = self.get_status_command(device_function);
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+ if status.contains(Status::CAPABILITIES_LIST) {
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+ Some((self.config_read_word(device_function, 0x34) & 0xFC) as u8)
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+ } else {
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+ None
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+ }
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+ }
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+}
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+
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+/// Information about a PCI Base Address Register.
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+#[derive(Clone, Debug, Eq, PartialEq)]
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+pub enum BarInfo {
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+ /// The BAR is for a memory region.
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+ Memory {
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+ /// The size of the BAR address and where it can be located.
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+ address_type: MemoryBarType,
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+ /// If true, then reading from the region doesn't have side effects. The CPU may cache reads
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+ /// and merge repeated stores.
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+ prefetchable: bool,
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+ /// The memory address, always 16-byte aligned.
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+ address: u64,
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+ /// The size of the BAR in bytes.
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+ size: u32,
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+ },
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+ /// The BAR is for an I/O region.
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+ IO {
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+ /// The I/O address, always 4-byte aligned.
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+ address: u32,
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+ /// The size of the BAR in bytes.
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+ size: u32,
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+ },
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+}
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+
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+impl BarInfo {
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+ /// Returns whether this BAR is a 64-bit memory region, and so takes two entries in the table in
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+ /// configuration space.
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+ pub fn takes_two_entries(&self) -> bool {
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+ matches!(
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+ self,
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+ BarInfo::Memory {
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+ address_type: MemoryBarType::Width64,
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+ ..
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+ }
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+ )
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+ }
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+
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+ /// Returns the address and size of this BAR if it is a memory bar, or `None` if it is an IO
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+ /// BAR.
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+ pub fn memory_address_size(&self) -> Option<(u64, u32)> {
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+ if let Self::Memory { address, size, .. } = self {
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+ Some((*address, *size))
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+ } else {
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+ None
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+ }
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+ }
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+}
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+
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+impl Display for BarInfo {
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+ fn fmt(&self, f: &mut Formatter<'_>) -> fmt::Result {
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+ match self {
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+ Self::Memory {
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+ address_type,
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+ prefetchable,
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+ address,
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+ size,
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+ } => write!(
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+ f,
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+ "Memory space at {:#010x}, size {}, type {:?}, prefetchable {}",
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+ address, size, address_type, prefetchable
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+ ),
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+ Self::IO { address, size } => {
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+ write!(f, "I/O space at {:#010x}, size {}", address, size)
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+ }
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+ }
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+ }
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+}
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+
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+/// The location allowed for a memory BAR.
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+#[derive(Copy, Clone, Debug, Eq, PartialEq)]
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+pub enum MemoryBarType {
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+ /// The BAR has a 32-bit address and can be mapped anywhere in 32-bit address space.
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+ Width32,
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+ /// The BAR must be mapped below 1MiB.
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+ Below1MiB,
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+ /// The BAR has a 64-bit address and can be mapped anywhere in 64-bit address space.
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+ Width64,
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+}
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+
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+impl From<MemoryBarType> for u8 {
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+ fn from(bar_type: MemoryBarType) -> Self {
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+ match bar_type {
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|
|
+ MemoryBarType::Width32 => 0,
|
|
|
+ MemoryBarType::Below1MiB => 1,
|
|
|
+ MemoryBarType::Width64 => 2,
|
|
|
+ }
|
|
|
+ }
|
|
|
+}
|
|
|
+
|
|
|
+impl TryFrom<u8> for MemoryBarType {
|
|
|
+ type Error = PciError;
|
|
|
+
|
|
|
+ fn try_from(value: u8) -> Result<Self, Self::Error> {
|
|
|
+ match value {
|
|
|
+ 0 => Ok(Self::Width32),
|
|
|
+ 1 => Ok(Self::Below1MiB),
|
|
|
+ 2 => Ok(Self::Width64),
|
|
|
+ _ => Err(PciError::InvalidBarType),
|
|
|
+ }
|
|
|
+ }
|
|
|
+}
|
|
|
+
|
|
|
+/// Iterator over capabilities for a device.
|
|
|
+#[derive(Debug)]
|
|
|
+pub struct CapabilityIterator<'a> {
|
|
|
+ root: &'a PciRoot,
|
|
|
+ device_function: DeviceFunction,
|
|
|
+ next_capability_offset: Option<u8>,
|
|
|
+}
|
|
|
+
|
|
|
+impl<'a> Iterator for CapabilityIterator<'a> {
|
|
|
+ type Item = CapabilityInfo;
|
|
|
+
|
|
|
+ fn next(&mut self) -> Option<Self::Item> {
|
|
|
+ let offset = self.next_capability_offset?;
|
|
|
+
|
|
|
+ // Read the first 4 bytes of the capability.
|
|
|
+ let capability_header = self.root.config_read_word(self.device_function, offset);
|
|
|
+ let id = capability_header as u8;
|
|
|
+ let next_offset = (capability_header >> 8) as u8;
|
|
|
+ let private_header = (capability_header >> 16) as u16;
|
|
|
+
|
|
|
+ self.next_capability_offset = if next_offset == 0 {
|
|
|
+ None
|
|
|
+ } else if next_offset < 64 || next_offset & 0x3 != 0 {
|
|
|
+ warn!("Invalid next capability offset {:#04x}", next_offset);
|
|
|
+ None
|
|
|
+ } else {
|
|
|
+ Some(next_offset)
|
|
|
+ };
|
|
|
+
|
|
|
+ Some(CapabilityInfo {
|
|
|
+ offset,
|
|
|
+ id,
|
|
|
+ private_header,
|
|
|
+ })
|
|
|
+ }
|
|
|
+}
|
|
|
+
|
|
|
+/// Information about a PCI device capability.
|
|
|
+#[derive(Debug, Copy, Clone, Eq, PartialEq)]
|
|
|
+pub struct CapabilityInfo {
|
|
|
+ /// The offset of the capability in the PCI configuration space of the device function.
|
|
|
+ pub offset: u8,
|
|
|
+ /// The ID of the capability.
|
|
|
+ pub id: u8,
|
|
|
+ /// The third and fourth bytes of the capability, to save reading them again.
|
|
|
+ pub private_header: u16,
|
|
|
+}
|
|
|
+
|
|
|
+/// An iterator which enumerates PCI devices and functions on a given bus.
|
|
|
+#[derive(Debug)]
|
|
|
+pub struct BusDeviceIterator {
|
|
|
+ /// This must only be used to read read-only fields, and must not be exposed outside this
|
|
|
+ /// module, because it uses the same CAM as the main `PciRoot` instance.
|
|
|
+ root: PciRoot,
|
|
|
+ next: DeviceFunction,
|
|
|
+}
|
|
|
+
|
|
|
+impl Iterator for BusDeviceIterator {
|
|
|
+ type Item = (DeviceFunction, DeviceFunctionInfo);
|
|
|
+
|
|
|
+ fn next(&mut self) -> Option<Self::Item> {
|
|
|
+ while self.next.device < MAX_DEVICES {
|
|
|
+ // Read the header for the current device and function.
|
|
|
+ let current = self.next;
|
|
|
+ let device_vendor = self.root.config_read_word(current, 0);
|
|
|
+
|
|
|
+ // Advance to the next device or function.
|
|
|
+ self.next.function += 1;
|
|
|
+ if self.next.function >= MAX_FUNCTIONS {
|
|
|
+ self.next.function = 0;
|
|
|
+ self.next.device += 1;
|
|
|
+ }
|
|
|
+
|
|
|
+ if device_vendor != INVALID_READ {
|
|
|
+ let class_revision = self.root.config_read_word(current, 8);
|
|
|
+ let device_id = (device_vendor >> 16) as u16;
|
|
|
+ let vendor_id = device_vendor as u16;
|
|
|
+ let class = (class_revision >> 24) as u8;
|
|
|
+ let subclass = (class_revision >> 16) as u8;
|
|
|
+ let prog_if = (class_revision >> 8) as u8;
|
|
|
+ let revision = class_revision as u8;
|
|
|
+ let bist_type_latency_cache = self.root.config_read_word(current, 12);
|
|
|
+ let header_type = HeaderType::from((bist_type_latency_cache >> 16) as u8 & 0x7f);
|
|
|
+ return Some((
|
|
|
+ current,
|
|
|
+ DeviceFunctionInfo {
|
|
|
+ vendor_id,
|
|
|
+ device_id,
|
|
|
+ class,
|
|
|
+ subclass,
|
|
|
+ prog_if,
|
|
|
+ revision,
|
|
|
+ header_type,
|
|
|
+ },
|
|
|
+ ));
|
|
|
+ }
|
|
|
+ }
|
|
|
+ None
|
|
|
+ }
|
|
|
+}
|
|
|
+
|
|
|
+/// An identifier for a PCI bus, device and function.
|
|
|
+#[derive(Copy, Clone, Debug, Eq, PartialEq)]
|
|
|
+pub struct DeviceFunction {
|
|
|
+ /// The PCI bus number, between 0 and 255.
|
|
|
+ pub bus: u8,
|
|
|
+ /// The device number on the bus, between 0 and 31.
|
|
|
+ pub device: u8,
|
|
|
+ /// The function number of the device, between 0 and 7.
|
|
|
+ pub function: u8,
|
|
|
+}
|
|
|
+
|
|
|
+impl DeviceFunction {
|
|
|
+ /// Returns whether the device and function numbers are valid, i.e. the device is between 0 and
|
|
|
+ /// 31, and the function is between 0 and 7.
|
|
|
+ pub fn valid(&self) -> bool {
|
|
|
+ self.device < 32 && self.function < 8
|
|
|
+ }
|
|
|
+}
|
|
|
+
|
|
|
+impl Display for DeviceFunction {
|
|
|
+ fn fmt(&self, f: &mut Formatter) -> fmt::Result {
|
|
|
+ write!(f, "{:02x}:{:02x}.{}", self.bus, self.device, self.function)
|
|
|
+ }
|
|
|
+}
|
|
|
+
|
|
|
+/// Information about a PCI device function.
|
|
|
+#[derive(Clone, Debug, Eq, PartialEq)]
|
|
|
+pub struct DeviceFunctionInfo {
|
|
|
+ /// The PCI vendor ID.
|
|
|
+ pub vendor_id: u16,
|
|
|
+ /// The PCI device ID.
|
|
|
+ pub device_id: u16,
|
|
|
+ /// The PCI class.
|
|
|
+ pub class: u8,
|
|
|
+ /// The PCI subclass.
|
|
|
+ pub subclass: u8,
|
|
|
+ /// The PCI programming interface byte.
|
|
|
+ pub prog_if: u8,
|
|
|
+ /// The PCI revision ID.
|
|
|
+ pub revision: u8,
|
|
|
+ /// The type of PCI device.
|
|
|
+ pub header_type: HeaderType,
|
|
|
+}
|
|
|
+
|
|
|
+impl Display for DeviceFunctionInfo {
|
|
|
+ fn fmt(&self, f: &mut Formatter) -> fmt::Result {
|
|
|
+ write!(
|
|
|
+ f,
|
|
|
+ "{:04x}:{:04x} (class {:02x}.{:02x}, rev {:02x}) {:?}",
|
|
|
+ self.vendor_id,
|
|
|
+ self.device_id,
|
|
|
+ self.class,
|
|
|
+ self.subclass,
|
|
|
+ self.revision,
|
|
|
+ self.header_type,
|
|
|
+ )
|
|
|
+ }
|
|
|
+}
|
|
|
+
|
|
|
+/// The type of a PCI device function header.
|
|
|
+#[derive(Copy, Clone, Debug, Eq, PartialEq)]
|
|
|
+pub enum HeaderType {
|
|
|
+ /// A normal PCI device.
|
|
|
+ Standard,
|
|
|
+ /// A PCI to PCI bridge.
|
|
|
+ PciPciBridge,
|
|
|
+ /// A PCI to CardBus bridge.
|
|
|
+ PciCardbusBridge,
|
|
|
+ /// Unrecognised header type.
|
|
|
+ Unrecognised(u8),
|
|
|
+}
|
|
|
+
|
|
|
+impl From<u8> for HeaderType {
|
|
|
+ fn from(value: u8) -> Self {
|
|
|
+ match value {
|
|
|
+ 0x00 => Self::Standard,
|
|
|
+ 0x01 => Self::PciPciBridge,
|
|
|
+ 0x02 => Self::PciCardbusBridge,
|
|
|
+ _ => Self::Unrecognised(value),
|
|
|
+ }
|
|
|
+ }
|
|
|
+}
|
Andrew Walbran