Utility functions now only in macros

src/aclint.rs

@@ -65,41 +65,6 @@ impl<C: Clint> CLINT<C> {
 
     const MTIME_OFFSET: usize = 0xBFF8;
 
-    /// Returns `true` if any CLINT-related interrupt is pending.
-    #[inline]
-    pub fn is_interrupting() -> bool {
-        Self::mswi_is_interrupting() || Self::mtimer_is_interrupting()
-    }
-
-    /// Returns `true` if a machine software interrupt is pending.
-    #[inline]
-    pub fn mswi_is_interrupting() -> bool {
-        mswi::MSWI::is_interrupting()
-    }
-
-    /// Returns `true` if Machine Software Interrupts are enabled.
-    /// This bit must be set for the `MSWI` to trigger machine software interrupts.
-    #[inline]
-    pub fn mswi_is_enabled() -> bool {
-        mswi::MSWI::is_enabled()
-    }
-
-    /// Enables machine software interrupts to let the `MSWI` peripheral trigger interrupts.
-    ///
-    /// # Safety
-    ///
-    /// Enabling the `MSWI` may break mask-based critical sections.
-    #[inline]
-    pub unsafe fn mswi_enable() {
-        mswi::MSWI::enable();
-    }
-
-    /// Disables machine software interrupts to prevent the `MSWI` peripheral from triggering interrupts.
-    #[inline]
-    pub fn mswi_disable() {
-        mswi::MSWI::disable();
-    }
-
     /// Returns the `MSWI` peripheral.
     #[inline]
     pub const fn mswi() -> mswi::MSWI {
@@ -107,35 +72,6 @@ impl<C: Clint> CLINT<C> {
         unsafe { mswi::MSWI::new(C::BASE) }
     }
 
-    /// Returns `true` if a machine timer interrupt is pending.
-    #[inline]
-    pub fn mtimer_is_interrupting() -> bool {
-        mtimer::MTIMER::is_interrupting()
-    }
-
-    /// Returns `true` if Machine Timer Interrupts are enabled.
-    /// This bit must be set for the `MTIMER` to trigger machine timer interrupts.
-    #[inline]
-    pub fn mtimer_is_enabled() -> bool {
-        mtimer::MTIMER::is_enabled()
-    }
-
-    /// Enables machine timer interrupts to let the `MTIMER` peripheral trigger interrupts.
-    ///
-    /// # Safety
-    ///
-    /// Enabling the `MTIMER` may break mask-based critical sections.
-    #[inline]
-    pub unsafe fn mtimer_enable() {
-        mtimer::MTIMER::enable();
-    }
-
-    /// Disables machine timer interrupts to prevent the `MTIMER` peripheral from triggering interrupts.
-    #[inline]
-    pub fn mtimer_disable() {
-        mtimer::MTIMER::disable();
-    }
-
     /// Returns the `MTIMER` peripheral.
     #[inline]
     pub const fn mtimer() -> mtimer::MTIMER {

src/aclint/mswi.rs

@@ -25,37 +25,6 @@ impl MSWI {
         }
     }
 
-    /// Returns `true` if a machine software interrupt is pending.
-    #[inline]
-    pub fn is_interrupting() -> bool {
-        riscv::register::mip::read().msoft()
-    }
-
-    /// Returns `true` if Machine Software Interrupts are enabled.
-    #[inline]
-    pub fn is_enabled() -> bool {
-        riscv::register::mie::read().msoft()
-    }
-
-    /// Sets the Machine Software Interrupt bit of the `mie` CSR.
-    /// This bit must be set for the `MSWI` to trigger machine software interrupts.
-    ///
-    /// # Safety
-    ///
-    /// Enabling the `MSWI` may break mask-based critical sections.
-    #[inline]
-    pub unsafe fn enable() {
-        riscv::register::mie::set_msoft();
-    }
-
-    /// Clears the Machine Software Interrupt bit of the `mie` CSR.
-    /// When cleared, the `MSWI` cannot trigger machine software interrupts.
-    #[inline]
-    pub fn disable() {
-        // SAFETY: it is safe to disable interrupts
-        unsafe { riscv::register::mie::clear_msoft() };
-    }
-
     /// Returns the `MSIP` register for the HART which ID is `hart_id`.
     ///
     /// # Note

src/aclint/mtimer.rs

@@ -27,37 +27,6 @@ impl MTIMER {
         }
     }
 
-    /// Returns `true` if a machine timer interrupt is pending.
-    #[inline]
-    pub fn is_interrupting() -> bool {
-        riscv::register::mip::read().mtimer()
-    }
-
-    /// Returns `true` if Machine Timer Interrupts are enabled.
-    #[inline]
-    pub fn is_enabled() -> bool {
-        riscv::register::mie::read().mtimer()
-    }
-
-    /// Sets the Machine Timer Interrupt bit of the `mie` CSR.
-    /// This bit must be set for the `MTIMER` to trigger machine timer interrupts.
-    ///
-    /// # Safety
-    ///
-    /// Enabling the `MTIMER` may break mask-based critical sections.
-    #[inline]
-    pub unsafe fn enable() {
-        riscv::register::mie::set_mtimer();
-    }
-
-    /// Clears the Machine Timer Interrupt bit of the `mie` CSR.
-    /// When cleared, the `MTIMER` cannot trigger machine timer interrupts.
-    #[inline]
-    pub fn disable() {
-        // SAFETY: it is safe to disable interrupts
-        unsafe { riscv::register::mie::clear_mtimer() };
-    }
-
     /// Returns the `MTIMECMP` register for the HART which ID is `hart_id`.
     ///
     /// # Note

src/lib.rs

@@ -3,10 +3,10 @@
 #![deny(missing_docs)]
 #![no_std]
 
-pub use riscv; // re-export riscv crate to allow users to use it without importing it
+pub use riscv; // re-export riscv crate to allow macros to use it
 
-pub mod common;
+pub mod common; // common definitions for all peripherals
 pub mod macros; // macros for easing the definition of peripherals in PACs
 
-pub mod aclint;
-pub mod plic;
+pub mod aclint; // ACLINT and CLINT peripherals
+pub mod plic; // PLIC peripheral

src/macros.rs

@@ -75,6 +75,47 @@ macro_rules! clint_codegen {
         }
 
         impl CLINT {
+            /// Returns `true` if a machine timer **OR** software interrupt is pending.
+            #[inline]
+            pub fn is_interrupting() -> bool {
+                Self::mswi_is_interrupting() || Self::mtimer_is_interrupting()
+            }
+
+            /// Returns `true` if machine timer **OR** software interrupts are enabled.
+            pub fn is_enabled() -> bool {
+                Self::mswi_is_enabled() || Self::mtimer_is_enabled()
+            }
+
+            /// Enables machine timer **AND** software interrupts to allow the CLINT to trigger interrupts.
+            ///
+            /// # Safety
+            ///
+            /// Enabling the `CLINT` may break mask-based critical sections.
+            #[inline]
+            pub unsafe fn enable() {
+                Self::mswi_enable();
+                Self::mtimer_enable();
+            }
+
+            /// Disables machine timer **AND** software interrupts to prevent the CLINT from triggering interrupts.
+            #[inline]
+            pub fn disable() {
+                Self::mswi_disable();
+                Self::mtimer_disable();
+            }
+
+            /// Returns `true` if a machine software interrupt is pending.
+            #[inline]
+            pub fn mswi_is_interrupting() -> bool {
+                $crate::riscv::register::mip::read().msoft()
+            }
+
+            /// Returns `true` if Machine Software Interrupts are enabled.
+            #[inline]
+            pub fn mswi_is_enabled() -> bool {
+                $crate::riscv::register::mie::read().msoft()
+            }
+
             /// Enables the `MSWI` peripheral.
             ///
             /// # Safety
@@ -82,35 +123,51 @@ macro_rules! clint_codegen {
             /// Enabling the `MSWI` may break mask-based critical sections.
             #[inline]
             pub unsafe fn mswi_enable() {
-                $crate::aclint::CLINT::<CLINT>::mswi_enable();
+                $crate::riscv::register::mie::set_msoft();
             }
 
             /// Disables the `MSWI` peripheral.
             #[inline]
             pub fn mswi_disable() {
-                $crate::aclint::CLINT::<CLINT>::mswi_disable();
+                // SAFETY: it is safe to disable interrupts
+                unsafe { $crate::riscv::register::mie::clear_msoft() };
+            }
+
+            /// Returns the `MSWI` peripheral.
+            #[inline]
+            pub const fn mswi() -> $crate::aclint::mswi::MSWI {
+                $crate::aclint::CLINT::<CLINT>::mswi()
+            }
+
+            /// Returns `true` if a machine timer interrupt is pending.
+            #[inline]
+            pub fn mtimer_is_interrupting() -> bool {
+                $crate::riscv::register::mip::read().mtimer()
+            }
+
+            /// Returns `true` if Machine Timer Interrupts are enabled.
+            #[inline]
+            pub fn mtimer_is_enabled() -> bool {
+                $crate::riscv::register::mie::read().mtimer()
             }
 
-            /// Enables the `MTIMER` peripheral.
+            /// Sets the Machine Timer Interrupt bit of the `mie` CSR.
+            /// This bit must be set for the `MTIMER` to trigger machine timer interrupts.
             ///
             /// # Safety
             ///
             /// Enabling the `MTIMER` may break mask-based critical sections.
             #[inline]
             pub unsafe fn mtimer_enable() {
-                $crate::aclint::CLINT::<CLINT>::mtimer_enable();
+                $crate::riscv::register::mie::set_mtimer();
             }
 
-            /// Disables the `MTIMER` peripheral.
+            /// Clears the Machine Timer Interrupt bit of the `mie` CSR.
+            /// When cleared, the `MTIMER` cannot trigger machine timer interrupts.
             #[inline]
-            pub fn disable_mtimer() {
-                $crate::aclint::CLINT::<CLINT>::mtimer_disable();
-            }
-
-            /// Returns the `MSWI` peripheral.
-            #[inline]
-            pub const fn mswi() -> $crate::aclint::mswi::MSWI {
-                $crate::aclint::CLINT::<CLINT>::mswi()
+            pub fn mtimer_disable() {
+                // SAFETY: it is safe to disable interrupts
+                unsafe { $crate::riscv::register::mie::clear_mtimer() };
             }
 
             /// Returns the `MTIMER` peripheral.
@@ -154,6 +211,18 @@ macro_rules! plic_codegen {
         }
 
         impl PLIC {
+            /// Returns `true` if a machine external interrupt is pending.
+            #[inline]
+            pub fn is_interrupting() -> bool {
+                $crate::riscv::register::mip::read().mext()
+            }
+
+            /// Returns true if Machine External Interrupts are enabled.
+            #[inline]
+            pub fn is_enabled() -> bool {
+                $crate::riscv::register::mie::read().mext()
+            }
+
             /// Enables machine external interrupts to allow the PLIC to trigger interrupts.
             ///
             /// # Safety
@@ -161,13 +230,14 @@ macro_rules! plic_codegen {
             /// Enabling the `PLIC` may break mask-based critical sections.
             #[inline]
             pub unsafe fn enable() {
-                $crate::plic::PLIC::<PLIC>::enable();
+                $crate::riscv::register::mie::set_mext();
             }
 
             /// Disables machine external interrupts to prevent the PLIC from triggering interrupts.
             #[inline]
             pub fn disable() {
-                $crate::plic::PLIC::<PLIC>::disable();
+                // SAFETY: it is safe to disable interrupts
+                unsafe { $crate::riscv::register::mie::clear_mext() };
             }
 
             /// Returns the priorities register of the PLIC.

src/plic.rs

@@ -127,37 +127,6 @@ impl<P: Plic> PLIC<P> {
 
     const PENDINGS_OFFSET: usize = 0x1000;
 
-    /// Returns `true` if a machine external interrupt is pending.
-    #[inline]
-    pub fn is_interrupting() -> bool {
-        riscv::register::mip::read().mext()
-    }
-
-    /// Returns true if Machine External Interrupts are enabled.
-    #[inline]
-    pub fn is_enabled() -> bool {
-        riscv::register::mie::read().mext()
-    }
-
-    /// Sets the Machine External Interrupt bit of the `mie` CSR.
-    /// This bit must be set for the PLIC to trigger machine external interrupts.
-    ///
-    /// # Safety
-    ///
-    /// Enabling the `PLIC` may break mask-based critical sections.
-    #[inline]
-    pub unsafe fn enable() {
-        riscv::register::mie::set_mext();
-    }
-
-    /// Clears the Machine External Interrupt bit of the `mie` CSR.
-    /// When cleared, the PLIC does not trigger machine external interrupts.
-    #[inline]
-    pub fn disable() {
-        // SAFETY: it is safe to disable interrupts
-        unsafe { riscv::register::mie::clear_mext() };
-    }
-
     /// Returns the priorities register of the PLIC.
     /// This register allows to set the priority level of each interrupt source.
     /// The priority level of each interrupt source is shared among all the contexts.