Refactor target_feature parsing

riscv-rt/build.rs

@@ -18,7 +18,7 @@ fn add_linker_script(arch_width: u32) -> io::Result<()> {
 }
 
 /// Parse the target RISC-V architecture and returns its bit width and the extension set
-fn parse_target(target: &str) -> (u32, HashSet<char>) {
+fn parse_target(target: &str, cargo_flags: &str) -> (u32, HashSet<char>) {
     // isolate bit width and extensions from the rest of the target information
     let arch = target
         .trim_start_matches("riscv")
@@ -43,30 +43,39 @@ fn parse_target(target: &str) -> (u32, HashSet<char>) {
         extensions.insert('d');
     }
 
-    (bits, extensions)
-}
-
-fn main() {
-    let target = env::var("TARGET").unwrap();
-    let _name = env::var("CARGO_PKG_NAME").unwrap();
-
-    // This is required until target_feature risc-v work is stable and in-use (rust 1.75.0)
-    let cargo_flags = env::var("CARGO_ENCODED_RUSTFLAGS").unwrap();
     let cargo_flags = cargo_flags
         .split(0x1fu8 as char)
         .filter(|arg| !arg.is_empty());
-    
-    let target_features = cargo_flags
+     
+    cargo_flags
         .filter(|k| k.starts_with("target-feature=")).flat_map(|str| {
             let flags = str.split('=').collect::<Vec<&str>>()[1];
             flags.split(',')
+        })
+        .for_each(|feature| {
+            let chars = feature.chars().collect::<Vec<char>>();
+            match chars[0] {
+                '+' => { extensions.insert(chars[1]); }
+                '-' => { extensions.remove(&chars[1]); }
+                _ => { panic!("Unsupported target feature operation"); }
+            }
         });
 
+    (bits, extensions)
+}
+
+fn main() {
+    let target = env::var("TARGET").unwrap();
+    let cargo_flags = env::var("CARGO_ENCODED_RUSTFLAGS").unwrap();
+    let _name = env::var("CARGO_PKG_NAME").unwrap();
+
     // set configuration flags depending on the target
     if target.starts_with("riscv") {
         println!("cargo:rustc-cfg=riscv");
 
-        let (bits, mut extensions) = parse_target(&target);
+        // This is required until target_arch & target_feature risc-v work is 
+        // stable and in-use (rust 1.75.0)
+        let (bits, extensions) = parse_target(&target, &cargo_flags);
 
         // generate the linker script and expose the ISA width
         let arch_width = match bits {
@@ -82,15 +91,6 @@ fn main() {
         };
         add_linker_script(arch_width).unwrap();
 
-        target_features.for_each(|feature| {
-            let chars = feature.chars().collect::<Vec<char>>();
-            if chars[0] == '+' {
-                extensions.insert(chars[1]);
-            } else if chars[0] == '-' {
-                extensions.remove(&chars[1]);
-            }
-        });
-
         // expose the ISA extensions
         for ext in &extensions {
             println!("cargo:rustc-cfg=riscv{}", ext);