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Low level access to RISC-V processors

Aborescence: 6a6c1cdba1
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riscv
mini-ninja-64 6a6c1cdba1 Refactor target_feature parsing il y a 1 an
.github 4ad4cfdbff Revert "support for S-mode interrupts" il y a 1 an
riscv 1e2f9862ef Additional updates to Rust 1.60.0 il y a 1 an
riscv-pac b68560da22 riscv-pac crate il y a 1 an
riscv-rt 6a6c1cdba1 Refactor target_feature parsing il y a 1 an
.gitignore 4344b03e88 Remove bit_field dependency il y a 1 an
CODE_OF_CONDUCT.md 4bd6d68552 Update link (riscv to risc-v) il y a 4 ans
Cargo.toml b68560da22 riscv-pac crate il y a 1 an
README.md fd0ecf0a93 forgot README il y a 1 an

README.md

RISC-V crates

This repository contains various crates useful for writing Rust programs on RISC-V microcontrollers:

  • riscv: CPU registers access and intrinsics
  • [riscv-pac]: Common traits to be implemented by RISC-V PACs
  • riscv-rt: Startup code and interrupt handling

This project is developed and maintained by the RISC-V team.

Contribution

Unless you explicitly state otherwise, any contribution intentionally submitted for inclusion in the work by you, as defined in the Apache-2.0 license, shall be dual licensed as above, without any additional terms or conditions.

Code of Conduct

Contribution to this crate is organized under the terms of the Rust Code of Conduct, the maintainer of this crate, the RISC-V team, promises to intervene to uphold that code of conduct.