Commit History

Author SHA1 Message Date
  Vadim Kaushan 061579f97e Call external functions when inline-asm is not set 6 years ago
  Vadim Kaushan 41378757c0 Do not require const-fn and asm features 6 years ago
  Vadim Kaushan 3652547073 Simplify #[cfg()] predicate expressions 6 years ago
  bors[bot] 86ac78b4aa Merge #15 6 years ago
  Vadim Kaushan 52ad774fc1 Remove useless cfg_attr 6 years ago
  Vadim Kaushan 921aa2bbec Refactoring: use new macros for M-mode CSRs 6 years ago
  bors[bot] 8bffbd7291 Merge #12 #14 6 years ago
  bors[bot] ca737e7a48 Merge #13 6 years ago
  Vadim Kaushan b790a0e92a Replace no-op with unimplemented!() 6 years ago
  Vadim Kaushan 9550fe0687 Remove ecall and *ret instructions from riscv::asm 6 years ago
  WangRunji 8776d30d3b add S-Mode registers 6 years ago
  WangRunji 9dc7b40fdd impl sfence_vma & sfence_vma_all 6 years ago
  bors[bot] 4e16dd85ed Merge #10 6 years ago
  bors[bot] 591b7df808 Merge #9 6 years ago
  bors[bot] 489b88f66b Merge #8 6 years ago
  M Farkas-Dyck 8e0faa9182 these raw instructions are unsafe 6 years ago
  M Farkas-Dyck 5a88960ee0 use `NonZeroUsize` where appropriate 6 years ago
  M Farkas-Dyck ecc69bda00 mepc is word-size 6 years ago
  David Craven 8d530616c9 Build master branch too. 6 years ago
  David Craven be2a15f34e Bump version and update url. 6 years ago
  David Craven b03aae8850 Update README. 6 years ago
  David Craven 5e55720ad8 Update bare-metal. 6 years ago
  David Craven 34b2ba33cd Add inline-asm feature. 6 years ago
  David Craven 59d46795b2 A unified contributing experience. 6 years ago
  Dan Callaghan 6769ac9262 fix target_arch conditionals to match "riscv32" and "riscv64" 6 years ago
  David Craven 87bcdd8bab Bump version. 7 years ago
  Jakob Weisblat 8597f1c32d Fix typo in register/misa.rs 7 years ago
  David Craven 45364b26a8 Add mepc register. 7 years ago
  David Craven cd5200c5fa Fix mstatus register value. 7 years ago
  David Craven 7db0e71060 New api. 7 years ago