 Vadim Kaushan
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1c716aacb1
Update 'riscv' dependency
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Vadim Kaushan
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8163823a83
Produce a compilation error if riscv-rt appears more than once in the dependency graph
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 bors[bot]
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fdc92f3d1c
Merge #30
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Vadim Kaushan
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e85c1fb81c
Bump version
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Vadim Kaushan
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f572fdecd4
Add MSRV policy
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Vadim Kaushan
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d2eff45f59
Fix documentation
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bors[bot]
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816b3ce66f
Merge #27
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Vadim Kaushan
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64fb6ad312
[macros] Remove 'exception' and 'interrupt' attributes
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Vadim Kaushan
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253aa88fff
[macros] Remove 'static mut' hack
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Vadim Kaushan
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f11f052390
Add 'pre_init' attribute
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Vadim Kaushan
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f981ee60ef
Use proc-macro `entry`
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Vadim Kaushan
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1ad79f8fb7
[macros] Replace cortex-m with riscv
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Vadim Kaushan
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85efa3b080
[macros] Fix Cargo.toml
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Vadim Kaushan
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06e15287c2
Copy cortex-m-rt-macros
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bors[bot]
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099033f22b
Merge #28
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Vadim Kaushan
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b7dac856be
Update 'riscv' dependency
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Vadim Kaushan
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465690eaa5
Regenerate binaries
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Vadim Kaushan
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d5e487fcf7
Update CI build matrix
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Vadim Kaushan
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656af9deaf
Regenerate binaries
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Vadim Kaushan
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6ef7218873
Generate binaries for riscv64 targets
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Vadim Kaushan
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28e5e7beb5
Disable relaxation for gp load
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Vadim Kaushan
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f88d31d88f
Use position-independent loads in asm.S
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bors[bot]
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cd42df7e2e
Merge #23
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Vadim Kaushan
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b4486cbb8c
Fix _start_trap alignment
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bors[bot]
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313f1666c2
Merge #22
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Vadim Kaushan
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0d671a419b
Fix _start_trap address calculation
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bors[bot]
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b68f38ef40
Merge #21
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Vadim Kaushan
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e4217a736c
Leave just team e-mail in authors
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Vadim Kaushan
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93c9d0ad31
Add team e-mail to authors
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bors[bot]
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40b4b80bc1
Merge #19
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