Commit History

Author SHA1 Message Date
  Vadim Kaushan a8040bd24b Check blobs in separate target 6 years ago
  Vadim Kaushan 9352831150 Simplify CI scripts 6 years ago
  Vadim Kaushan 41b4c1c1e6 Remove useless 'set' commands 6 years ago
  Vadim Kaushan 662dcb67d2 Update Travis build matrix 6 years ago
  Vadim Kaushan 8163823a83 Produce a compilation error if riscv-rt appears more than once in the dependency graph 6 years ago
  bors[bot] fdc92f3d1c Merge #30 6 years ago
  Vadim Kaushan e85c1fb81c Bump version 6 years ago
  Vadim Kaushan f572fdecd4 Add MSRV policy 6 years ago
  Vadim Kaushan d2eff45f59 Fix documentation 6 years ago
  bors[bot] 816b3ce66f Merge #27 6 years ago
  Vadim Kaushan 64fb6ad312 [macros] Remove 'exception' and 'interrupt' attributes 6 years ago
  Vadim Kaushan 253aa88fff [macros] Remove 'static mut' hack 6 years ago
  Vadim Kaushan f11f052390 Add 'pre_init' attribute 6 years ago
  Vadim Kaushan f981ee60ef Use proc-macro `entry` 6 years ago
  Vadim Kaushan 1ad79f8fb7 [macros] Replace cortex-m with riscv 6 years ago
  Vadim Kaushan 85efa3b080 [macros] Fix Cargo.toml 6 years ago
  Vadim Kaushan 06e15287c2 Copy cortex-m-rt-macros 6 years ago
  bors[bot] 099033f22b Merge #28 6 years ago
  Vadim Kaushan b7dac856be Update 'riscv' dependency 6 years ago
  Vadim Kaushan 465690eaa5 Regenerate binaries 6 years ago
  Vadim Kaushan d5e487fcf7 Update CI build matrix 6 years ago
  Vadim Kaushan 656af9deaf Regenerate binaries 6 years ago
  Vadim Kaushan 6ef7218873 Generate binaries for riscv64 targets 6 years ago
  Vadim Kaushan 28e5e7beb5 Disable relaxation for gp load 6 years ago
  Vadim Kaushan f88d31d88f Use position-independent loads in asm.S 6 years ago
  bors[bot] 2450868523 Merge #21 6 years ago
  Vadim Kaushan a091d236dd Bump version 6 years ago
  Vadim Kaushan 925c496949 Read composite CSRs as one 64-bit value 6 years ago
  Vadim Kaushan b665adeb95 Refactoring: use get_bit() instead of shifts 6 years ago
  Vadim Kaushan ab15a6a8c7 CI: check new targets 6 years ago