Low level access to RISC-V processors

Vadim Kaushan 04f472c434 Fix copyright year il y a 3 ans
.github 0b28f192f6 Add inline-asm build to CI, fix build il y a 3 ans
bin 96da9e2539 Remove riscv target post fix triple information from asm archive il y a 3 ans
src 2de8fc5930 fix in(reg) real_cyc in asm.rs il y a 3 ans
.gitignore a51143d366 Implement asm functions il y a 6 ans
CHANGELOG.md daf019cd7f Update CHANGELOG.md il y a 3 ans
CODE_OF_CONDUCT.md 4bd6d68552 Update link (riscv to risc-v) il y a 4 ans
Cargo.toml 8529d1e804 add asm::nop, asm::delay, and delay.rs. il y a 3 ans
README.md 04f472c434 Fix copyright year il y a 3 ans
asm.S 8529d1e804 add asm::nop, asm::delay, and delay.rs. il y a 3 ans
asm.h a659a0cc39 Declare all the CSR registers in asm.S il y a 5 ans
assemble.ps1 96da9e2539 Remove riscv target post fix triple information from asm archive il y a 3 ans
assemble.sh 96da9e2539 Remove riscv target post fix triple information from asm archive il y a 3 ans
build.rs 96da9e2539 Remove riscv target post fix triple information from asm archive il y a 3 ans
check-blobs.sh a51143d366 Implement asm functions il y a 6 ans

README.md

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riscv

Low level access to RISC-V processors

This project is developed and maintained by the RISC-V team.

Documentation

Minimum Supported Rust Version (MSRV)

This crate is guaranteed to compile on stable Rust 1.42.0 and up. It might compile with older versions but that may change in any new patch release.

License

Copyright 2019-2022 RISC-V team

Permission to use, copy, modify, and/or distribute this software for any purpose with or without fee is hereby granted, provided that the above copyright notice and this permission notice appear in all copies.

THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.

Code of Conduct

Contribution to this crate is organized under the terms of the Rust Code of Conduct, the maintainer of this crate, the RISC-V team, promises to intervene to uphold that code of conduct.