Low level access to RISC-V processors

Ilya Epifanov 0b1131dd20 Only checking for necessary extensions when linking 4 anos atrás
.github 59d46795b2 A unified contributing experience. 6 anos atrás
bin 0b1131dd20 Only checking for necessary extensions when linking 4 anos atrás
ci 698cb306ea Enable gcc caching 6 anos atrás
src 54a0364304 register: add vexriscv-specific registers 5 anos atrás
.gitignore a51143d366 Implement asm functions 6 anos atrás
.travis.yml 7d4919a67c Add MSRV policy 6 anos atrás
CHANGELOG.md 99e189199b Release v0.5.6 5 anos atrás
CODE_OF_CONDUCT.md c1a3fe2dd9 Rename RISCV to RISC-V 6 anos atrás
Cargo.toml 0b1131dd20 Only checking for necessary extensions when linking 4 anos atrás
README.md c1a3fe2dd9 Rename RISCV to RISC-V 6 anos atrás
asm.S 54a0364304 register: add vexriscv-specific registers 5 anos atrás
asm.h a659a0cc39 Declare all the CSR registers in asm.S 5 anos atrás
assemble.ps1 0b1131dd20 Only checking for necessary extensions when linking 4 anos atrás
assemble.sh 0b1131dd20 Only checking for necessary extensions when linking 4 anos atrás
build.rs 0b1131dd20 Only checking for necessary extensions when linking 4 anos atrás
check-blobs.sh a51143d366 Implement asm functions 6 anos atrás

README.md

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riscv

Low level access to RISC-V processors

This project is developed and maintained by the RISC-V team.

Documentation

License

Copyright 2019 RISC-V team

Permission to use, copy, modify, and/or distribute this software for any purpose with or without fee is hereby granted, provided that the above copyright notice and this permission notice appear in all copies.

THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.

Code of Conduct

Contribution to this crate is organized under the terms of the Rust Code of Conduct, the maintainer of this crate, the RISC-V team, promises to intervene to uphold that code of conduct.