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Low level access to RISC-V processors

Román Cárdenas 173ea431c3 fix single-hart 1 жил өмнө
.github f3e755efa0 move all assembly to asm.rs 1 жил өмнө
riscv c6231cedbc bug fix 1 жил өмнө
riscv-pac b68560da22 riscv-pac crate 1 жил өмнө
riscv-rt 173ea431c3 fix single-hart 1 жил өмнө
riscv-semihosting f98f303ed3 Update riscv-semihosting/src/lib.rs 1 жил өмнө
.gitignore 4344b03e88 Remove bit_field dependency 1 жил өмнө
CODE_OF_CONDUCT.md 4bd6d68552 Update link (riscv to risc-v) 4 жил өмнө
Cargo.toml e70afe47bd adjust the workspace 1 жил өмнө
README.md e70afe47bd adjust the workspace 1 жил өмнө

README.md

RISC-V crates

This repository contains various crates useful for writing Rust programs on RISC-V microcontrollers:

  • riscv: CPU registers access and intrinsics
  • riscv-pac: Common traits to be implemented by RISC-V PACs
  • riscv-rt: Startup code and interrupt handling
  • riscv-semihosting: Semihosting for RISC-V processors

This project is developed and maintained by the RISC-V team.

Contribution

Unless you explicitly state otherwise, any contribution intentionally submitted for inclusion in the work by you, as defined in the Apache-2.0 license, shall be dual licensed as above, without any additional terms or conditions.

Code of Conduct

Contribution to this crate is organized under the terms of the Rust Code of Conduct, the maintainer of this crate, the RISC-V team, promises to intervene to uphold that code of conduct.