Low level access to RISC-V processors

Aaron Gowatch 1e2f9862ef Additional updates to Rust 1.60.0 1 éve
.github 1e2f9862ef Additional updates to Rust 1.60.0 1 éve
riscv 1e2f9862ef Additional updates to Rust 1.60.0 1 éve
riscv-rt 1e2f9862ef Additional updates to Rust 1.60.0 1 éve
.gitignore 4344b03e88 Remove bit_field dependency 1 éve
CODE_OF_CONDUCT.md 4bd6d68552 Update link (riscv to risc-v) 4 éve
Cargo.toml cd474dda9c Setting CI (WIP) 1 éve
README.md 5407f3826e Addressing review 1 éve

README.md

RISC-V crates

This repository contains various crates useful for writing Rust programs on RISC-V microcontrollers:

  • riscv: CPU peripheral access and intrinsics
  • riscv-rt: Startup code and interrupt handling

This project is developed and maintained by the RISC-V team.

Contribution

Unless you explicitly state otherwise, any contribution intentionally submitted for inclusion in the work by you, as defined in the Apache-2.0 license, shall be dual licensed as above, without any additional terms or conditions.

Code of Conduct

Contribution to this crate is organized under the terms of the Rust Code of Conduct, the maintainer of this crate, the RISC-V team, promises to intervene to uphold that code of conduct.