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Low level access to RISC-V processors

Дрво: 255ef60f1a
Гране Ознаке
riscv
bors[bot] 255ef60f1a Merge #38 пре 5 година
.github 59d46795b2 A unified contributing experience. пре 6 година
bin 8f7f5412e9 bin: rebuild asm file with vexriscv instructions пре 5 година
ci 698cb306ea Enable gcc caching пре 6 година
src 54a0364304 register: add vexriscv-specific registers пре 5 година
.gitignore a51143d366 Implement asm functions пре 6 година
.travis.yml 7d4919a67c Add MSRV policy пре 6 година
CHANGELOG.md 99e189199b Release v0.5.6 пре 5 година
CODE_OF_CONDUCT.md c1a3fe2dd9 Rename RISCV to RISC-V пре 6 година
Cargo.toml 99e189199b Release v0.5.6 пре 5 година
README.md c1a3fe2dd9 Rename RISCV to RISC-V пре 6 година
asm.S 54a0364304 register: add vexriscv-specific registers пре 5 година
asm.h a659a0cc39 Declare all the CSR registers in asm.S пре 5 година
assemble.ps1 f54f90f31c assemble: add powershell script пре 5 година
assemble.sh b53e0a5cd2 add riscv32i target пре 5 година
build.rs a51143d366 Implement asm functions пре 6 година
check-blobs.sh a51143d366 Implement asm functions пре 6 година

README.md

crates.io crates.io Build Status

riscv

Low level access to RISC-V processors

This project is developed and maintained by the RISC-V team.

Documentation

License

Copyright 2019 RISC-V team

Permission to use, copy, modify, and/or distribute this software for any purpose with or without fee is hereby granted, provided that the above copyright notice and this permission notice appear in all copies.

THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.

Code of Conduct

Contribution to this crate is organized under the terms of the Rust Code of Conduct, the maintainer of this crate, the RISC-V team, promises to intervene to uphold that code of conduct.