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Low level access to RISC-V processors

Drzewo: 2d0f35216d
Gałęzie Tagi
riscv
jakezhu9 2d0f35216d lib: update dependency embedded-hal to 1.0.0 1 rok temu
.github 4dc63f6743 minor changes 1 rok temu
riscv 2d0f35216d lib: update dependency embedded-hal to 1.0.0 1 rok temu
riscv-pac b68560da22 riscv-pac crate 1 rok temu
riscv-rt b8f0523d16 add links to Cargo.toml 1 rok temu
riscv-semihosting 2d0f35216d lib: update dependency embedded-hal to 1.0.0 1 rok temu
.gitignore 4344b03e88 Remove bit_field dependency 1 rok temu
CODE_OF_CONDUCT.md 4bd6d68552 Update link (riscv to risc-v) 4 lat temu
Cargo.toml e70afe47bd adjust the workspace 1 rok temu
README.md e70afe47bd adjust the workspace 1 rok temu

README.md

RISC-V crates

This repository contains various crates useful for writing Rust programs on RISC-V microcontrollers:

  • riscv: CPU registers access and intrinsics
  • riscv-pac: Common traits to be implemented by RISC-V PACs
  • riscv-rt: Startup code and interrupt handling
  • riscv-semihosting: Semihosting for RISC-V processors

This project is developed and maintained by the RISC-V team.

Contribution

Unless you explicitly state otherwise, any contribution intentionally submitted for inclusion in the work by you, as defined in the Apache-2.0 license, shall be dual licensed as above, without any additional terms or conditions.

Code of Conduct

Contribution to this crate is organized under the terms of the Rust Code of Conduct, the maintainer of this crate, the RISC-V team, promises to intervene to uphold that code of conduct.