riscv

riscv-semihosting

Semihosting for RISC-V processors

This is a fork of the cortex-m-semihosting crate with minimal changes to support the RISC-V Semihosting Specification as documented here

This crate can be used in exactly the same way as cortex-m-semihosting, simply by changing calls to cortex_m_semihosting::* to riscv_semihosting::*.

The rest of this document is as-is from upstream, and obviously any ARM-specific sections should be ignored.

This project is developed and maintained by the Cortex-M team.

Documentation

Minimum Supported Rust Version (MSRV)

This crate is guaranteed to compile on stable Rust 1.33.0 and up. It might compile with older versions but that may change in any new patch release.

License

Licensed under either of

• Apache License, Version 2.0 (LICENSE-APACHE or http://www.apache.org/licenses/LICENSE-2.0)
• MIT license (LICENSE-MIT or http://opensource.org/licenses/MIT)

at your option.

Contribution

Unless you explicitly state otherwise, any contribution intentionally submitted for inclusion in the work by you, as defined in the Apache-2.0 license, shall be dual licensed as above, without any additional terms or conditions.

Code of Conduct

Contribution to this crate is organized under the terms of the Rust Code of Conduct, the maintainer of this crate, the Cortex-M team, promises to intervene to uphold that code of conduct.