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riscv
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Low level access to RISC-V processors

Árbore: 622f6fe775
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riscv
Aleš Katona 622f6fe775 Merge pull request #139 from rust-embedded/interrupts-exceptions hai 1 ano
.github a733d0857f Delete bors.toml hai 1 ano
src 55f886e4c4 Rework in mcause and scause hai 1 ano
.gitignore bedccccfc6 mcause done hai 1 ano
CHANGELOG.md 6ba456a3c0 Forgot the changelog hai 1 ano
CODE_OF_CONDUCT.md 4bd6d68552 Update link (riscv to risc-v) %!s(int64=4) %!d(string=hai) anos
Cargo.toml 9ea5009726 cleaning commit history %!s(int64=2) %!d(string=hai) anos
README.md 780443991e Remove inline-asm feature and update MSRV to 1.59 %!s(int64=3) %!d(string=hai) anos
build.rs 780443991e Remove inline-asm feature and update MSRV to 1.59 %!s(int64=3) %!d(string=hai) anos

README.md

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riscv

Low level access to RISC-V processors

This project is developed and maintained by the RISC-V team.

Documentation

Minimum Supported Rust Version (MSRV)

This crate is guaranteed to compile on stable Rust 1.59 and up. It might compile with older versions but that may change in any new patch release.

License

Copyright 2019-2022 RISC-V team

Permission to use, copy, modify, and/or distribute this software for any purpose with or without fee is hereby granted, provided that the above copyright notice and this permission notice appear in all copies.

THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.

Code of Conduct

Contribution to this crate is organized under the terms of the Rust Code of Conduct, the maintainer of this crate, the RISC-V team, promises to intervene to uphold that code of conduct.