Low level access to RISC-V processors

Román Cárdenas Rodríguez ac437cba2a Merge pull request #183 from rust-embedded/fix-nightly-build hai 1 ano
.github 358a15264d tweak CI hai 1 ano
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riscv-pac 2531e682f3 MSRV is now 1.75 hai 1 ano
riscv-peripheral e9cd65d847 added example for async delays with CLINT hai 1 ano
riscv-rt 146258b428 FIx nightly builds hai 1 ano
riscv-semihosting 3384fc8b19 Prepare for releases hai 1 ano
.gitignore 4344b03e88 Remove bit_field dependency hai 1 ano
CODE_OF_CONDUCT.md 4bd6d68552 Update link (riscv to risc-v) %!s(int64=4) %!d(string=hai) anos
Cargo.toml b2183c696b Merge branch 'master' into add-peripheral hai 1 ano
README.md b2183c696b Merge branch 'master' into add-peripheral hai 1 ano

README.md

RISC-V crates

This repository contains various crates useful for writing Rust programs on RISC-V microcontrollers:

This project is developed and maintained by the RISC-V team.

Contribution

Unless you explicitly state otherwise, any contribution intentionally submitted for inclusion in the work by you, as defined in the Apache-2.0 license, shall be dual licensed as above, without any additional terms or conditions.

Code of Conduct

Contribution to this crate is organized under the terms of the Rust Code of Conduct, the maintainer of this crate, the RISC-V team, promises to intervene to uphold that code of conduct.