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Low level access to RISC-V processors

Drzewo: cd31989ba1
Gałęzie Tagi
riscv
bors[bot] cd31989ba1 Merge #95 3 lat temu
.github 0b28f192f6 Add inline-asm build to CI, fix build 3 lat temu
bin 96da9e2539 Remove riscv target post fix triple information from asm archive 3 lat temu
src f62fddc32a does not use `#[inline(always)]` for non-trivial functions 3 lat temu
.gitignore a51143d366 Implement asm functions 6 lat temu
CHANGELOG.md cf65f7569e csr: inline register reads and type conversations 3 lat temu
CODE_OF_CONDUCT.md 4bd6d68552 Update link (riscv to risc-v) 4 lat temu
Cargo.toml 8529d1e804 add asm::nop, asm::delay, and delay.rs. 3 lat temu
README.md 04f472c434 Fix copyright year 3 lat temu
asm.S 8529d1e804 add asm::nop, asm::delay, and delay.rs. 3 lat temu
asm.h a659a0cc39 Declare all the CSR registers in asm.S 5 lat temu
assemble.ps1 96da9e2539 Remove riscv target post fix triple information from asm archive 3 lat temu
assemble.sh 96da9e2539 Remove riscv target post fix triple information from asm archive 3 lat temu
build.rs 96da9e2539 Remove riscv target post fix triple information from asm archive 3 lat temu
check-blobs.sh a51143d366 Implement asm functions 6 lat temu

README.md

crates.io crates.io Build Status

riscv

Low level access to RISC-V processors

This project is developed and maintained by the RISC-V team.

Documentation

Minimum Supported Rust Version (MSRV)

This crate is guaranteed to compile on stable Rust 1.42.0 and up. It might compile with older versions but that may change in any new patch release.

License

Copyright 2019-2022 RISC-V team

Permission to use, copy, modify, and/or distribute this software for any purpose with or without fee is hereby granted, provided that the above copyright notice and this permission notice appear in all copies.

THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.

Code of Conduct

Contribution to this crate is organized under the terms of the Rust Code of Conduct, the maintainer of this crate, the RISC-V team, promises to intervene to uphold that code of conduct.