Low level access to RISC-V processors

Román Cárdenas Rodríguez d9b9df36e1 Merge pull request #171 from rust-embedded/semihosting		1 年之前
.github	4dc63f6743 minor changes	1 年之前
riscv	c6231cedbc bug fix	1 年之前
riscv-pac	b68560da22 riscv-pac crate	1 年之前
riscv-rt	045220785c Merge pull request #166 from mini-ninja-64/add-fpu-support	1 年之前
riscv-semihosting	f98f303ed3 Update riscv-semihosting/src/lib.rs	1 年之前
.gitignore	4344b03e88 Remove bit_field dependency	1 年之前
CODE_OF_CONDUCT.md	4bd6d68552 Update link (riscv to risc-v)	4 年之前
Cargo.toml	e70afe47bd adjust the workspace	1 年之前
README.md	e70afe47bd adjust the workspace	1 年之前

RISC-V crates

This repository contains various crates useful for writing Rust programs on RISC-V microcontrollers:

riscv: CPU registers access and intrinsics
riscv-pac: Common traits to be implemented by RISC-V PACs
riscv-rt: Startup code and interrupt handling
riscv-semihosting: Semihosting for RISC-V processors

This project is developed and maintained by the RISC-V team.

Contribution

Unless you explicitly state otherwise, any contribution intentionally submitted for inclusion in the work by you, as defined in the Apache-2.0 license, shall be dual licensed as above, without any additional terms or conditions.

Code of Conduct

Contribution to this crate is organized under the terms of the Rust Code of Conduct, the maintainer of this crate, the RISC-V team, promises to intervene to uphold that code of conduct.

README.md

RISC-V crates

Contribution

Code of Conduct