Low level access to RISC-V processors

Vadim Kaushan e07d797ac9 Merge pull request #2 from FawazTirmizi/cortex-feature-parity il y a 2 ans
ci bab5fba9a7 add CI il y a 7 ans
src bf2940f069 Removed inline asm, bumped MSRV il y a 2 ans
.gitignore a8c058f0ee initial commit il y a 8 ans
.travis.yml 4e7d9d41b4 don't test master il y a 7 ans
CHANGELOG.md 4e8ad013fd Merge upstream cortex-m-semihosting. il y a 3 ans
Cargo.toml bf2940f069 Removed inline asm, bumped MSRV il y a 2 ans
LICENSE-APACHE a8c058f0ee initial commit il y a 8 ans
LICENSE-MIT a8c058f0ee initial commit il y a 8 ans
README.md bf2940f069 Removed inline asm, bumped MSRV il y a 2 ans

README.md

crates.io crates.io

cortex-m-semihosting

Semihosting for ARM Cortex-M processors

This project is developed and maintained by the Cortex-M team.

Documentation

Minimum Supported Rust Version (MSRV)

This crate is guaranteed to compile on stable Rust 1.59.0 and up. It won't compile with older versions.

License

Licensed under either of

at your option.

Contribution

Unless you explicitly state otherwise, any contribution intentionally submitted for inclusion in the work by you, as defined in the Apache-2.0 license, shall be dual licensed as above, without any additional terms or conditions.

Code of Conduct

Contribution to this crate is organized under the terms of the Rust Code of Conduct, the maintainer of this crate, the Cortex-M team, promises to intervene to uphold that code of conduct.