Low level access to RISC-V processors
Fawaz Tirmizi
f4c48301dd
Remove cortex-m-semihosting CI
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2 年 前 | |
|---|---|---|
| src | 2 年 前 | |
| .gitignore | 8 年 前 | |
| .travis.yml | 7 年 前 | |
| CHANGELOG.md | 2 年 前 | |
| Cargo.toml | 2 年 前 | |
| LICENSE-APACHE | 8 年 前 | |
| LICENSE-MIT | 8 年 前 | |
| README.md | 2 年 前 |
README.md
riscv-semihosting
Semihosting for RISC-V processors
This is a fork of the cortex-m-semihosting crate with changes to support the RISC-V Semihosting Specification as documented here
This crate can be used in exactly the same way as cortex-m-semihosting, simply
by changing calls to cortex_m_semihosting::* to riscv_semihosting::*. Given
this, the
cortex-m-semihosting documentation is
generally sufficient for using this library.
Minimum Supported Rust Version (MSRV)
This crate is guaranteed to compile on stable Rust 1.59.0 and up. It won't compile with older versions.
License
Licensed under either of
- Apache License, Version 2.0 (LICENSE-APACHE or http://www.apache.org/licenses/LICENSE-2.0)
- MIT license (LICENSE-MIT or http://opensource.org/licenses/MIT)
at your option.
Contribution
Unless you explicitly state otherwise, any contribution intentionally submitted for inclusion in the work by you, as defined in the Apache-2.0 license, shall be dual licensed as above, without any additional terms or conditions.
Code of Conduct
Contribution to this crate is organized under the terms of the Rust Code of Conduct, the maintainer of this crate, the RISC-V team, promises to intervene to uphold that code of conduct.