Low level access to RISC-V processors

LoGin 4241a97627 feat: Add update_sum method to Sstatus struct (#8)		7 月之前
.github	afddf094a0 Merge branch 'master' of github.com:rust-embedded/riscv into riscv-rt-asm	9 月之前
riscv	4241a97627 feat: Add update_sum method to Sstatus struct (#8)	7 月之前
riscv-pac	cadabef94f Minor releases	9 月之前
riscv-peripheral	d51c622ca8 Cargo metadata for riscv-peripheral	9 月之前
riscv-rt	6cab675051 Patch merge origin 240405 (#5)	8 月之前
riscv-semihosting	3384fc8b19 Prepare for releases	10 月之前
.gitignore	4344b03e88 Remove bit_field dependency	1 年之前
CODE_OF_CONDUCT.md	4bd6d68552 Update link (riscv to risc-v)	4 年之前
Cargo.toml	b2183c696b Merge branch 'master' into add-peripheral	10 月之前
README.md	b2183c696b Merge branch 'master' into add-peripheral	10 月之前

RISC-V crates

This repository contains various crates useful for writing Rust programs on RISC-V microcontrollers:

riscv: CPU registers access and intrinsics
riscv-pac: Common traits to be implemented by RISC-V PACs
riscv-peripheral: Interfaces for standard RISC-V peripherals
riscv-rt: Startup code and interrupt handling
riscv-semihosting: Semihosting for RISC-V processors

This project is developed and maintained by the RISC-V team.

Contribution

Unless you explicitly state otherwise, any contribution intentionally submitted for inclusion in the work by you, as defined in the Apache-2.0 license, shall be dual licensed as above, without any additional terms or conditions.

Code of Conduct

Contribution to this crate is organized under the terms of the Rust Code of Conduct, the maintainer of this crate, the RISC-V team, promises to intervene to uphold that code of conduct.

README.md

RISC-V crates

Contribution

Code of Conduct