Use new stabilized asm! macro

Pull request: https://github.com/rust-lang/rust/pull/91728

Does not require asm_sym and asm_const

.vscode/settings.json

@@ -0,0 +1,10 @@
+{   
+    // Prevent error "can't find crate for `test`" in no_std
+    // Ref: https://github.com/rust-lang/vscode-rust/issues/729
+    // For vscode-rust plugin user:
+    "rust.target": "riscv64imac-unknown-none-elf",
+    "rust.all_targets": false,
+    // For Rust Analyzer:
+    "rust-analyzer.cargo.target": "riscv64imac-unknown-none-elf",
+    "rust-analyzer.checkOnSave.allTargets": false
+}

CHANGELOG.md

@@ -14,6 +14,7 @@ and this project adheres to [Semantic Versioning](https://semver.org/spec/v2.0.0
 - Support SBI v0.3 hart suspend function
 - Support PMU extension trait and init function
 - Use fat pointer cell to support asynchronous hart state monitor module
+- Build under new asm! macro
 
 ### Modified
 - Reform RustSBI project into a library

Cargo.toml

@@ -20,8 +20,7 @@ edition = "2018"
 [package.metadata.docs.rs]
 default-target = "riscv64imac-unknown-none-elf"
 targets = [
-    "riscv32i-unknown-none-elf", "riscv32imc-unknown-none-elf", "riscv32imac-unknown-none-elf",
-    "riscv64imac-unknown-none-elf",
+    "riscv32imac-unknown-none-elf", "riscv64imac-unknown-none-elf",
 ]
 
 [dependencies]

src/hart_mask.rs

@@ -59,7 +59,7 @@ unsafe fn get_vaddr_usize(vaddr_ptr: *const usize) -> usize {
         #[cfg(target_arch = "riscv32")]
         () => {
             let mut ans: usize;
-            asm!("
+            core::arch::asm!("
                 li      {tmp}, (1 << 17)
                 csrrs   {tmp}, mstatus, {tmp}
                 lw      {ans}, 0({vmem})
@@ -70,7 +70,7 @@ unsafe fn get_vaddr_usize(vaddr_ptr: *const usize) -> usize {
         #[cfg(target_arch = "riscv64")]
         () => {
             let mut ans: usize;
-            asm!("
+            core::arch::asm!("
                 li      {tmp}, (1 << 17)
                 csrrs   {tmp}, mstatus, {tmp}
                 ld      {ans}, 0({vmem})
@@ -81,7 +81,7 @@ unsafe fn get_vaddr_usize(vaddr_ptr: *const usize) -> usize {
         #[cfg(target_arch = "riscv128")]
         () => {
             let mut ans: usize;
-            asm!("
+            core::arch::asm!("
                 li      {tmp}, (1 << 17)
                 csrrs   {tmp}, mstatus, {tmp}
                 lq      {ans}, 0({vmem})

src/lib.rs

@@ -137,7 +137,6 @@
 //! RustSBI provides implementations on common platforms in separate platform crates.
 
 #![no_std]
-#![feature(asm, asm_const, asm_sym)]
 #![feature(ptr_metadata)]
 
 extern crate alloc;

src/privileged.rs

@@ -25,17 +25,11 @@
 /// ```
 #[inline]
 pub unsafe fn enter_privileged(mhartid: usize, opaque: usize) -> ! {
-    match () {
-        #[cfg(any(target_arch = "riscv32", target_arch = "riscv64"))]
-        () => asm!("
-            csrrw   sp, mscratch, sp
-            mret
-        ", in("a0") mhartid, in("a1") opaque, options(nomem, noreturn)),
-        #[cfg(not(any(target_arch = "riscv32", target_arch = "riscv64")))]
-        () => {
-            drop(mhartid);
-            drop(opaque);
-            unimplemented!("not RISC-V instruction set architecture")
-        }
-    }
+    core::arch::asm!(
+        "csrrw  sp, mscratch, sp",
+        "mret",
+        in("a0") mhartid,
+        in("a1") opaque,
+        options(nomem, noreturn)
+    )
 }

src/util.rs

@@ -4,6 +4,7 @@
 
 use alloc::boxed::Box;
 use core::{
+    arch::asm,
     cell::UnsafeCell,
     fmt::{self, Debug},
     marker::PhantomData,
@@ -114,12 +115,6 @@ impl<T: ?Sized> OnceFatBox<T> {
     }
 }
 
-// // FIXME: use `core::arch::riscv::pause()` after https://github.com/rust-lang/rust/pull/91548
-// #[inline]
-// fn pause() {
-//     unsafe { asm!(".word 0x0100000F", options(nomem, nostack)) }
-// }
-
 unsafe impl<T: Sync + Send + ?Sized> Sync for OnceFatBox<T> {}
 
 /// Use only amo instructions on mutex; no lr/sc instruction is used