 dkhayes117
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4be384d0cd
More formatting :(
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4 years ago |
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dkhayes117
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8a36b3e3d6
Cargo fmt
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4 years ago |
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dkhayes117
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6878e5f774
Fix weird formatting in mod.rs
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4 years ago |
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dkhayes117
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f273ef59b1
Run cargo fmt again in register directory
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4 years ago |
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dkhayes117
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42fa92f501
Fix with Cargo fmt
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4 years ago |
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dkhayes117
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282345f3de
Fix Comments on user accesses: cycle.rs, cycleh.rs, instret.rs, and instreth.rs
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4 years ago |
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dkhayes117
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ab0777651d
Fix typos
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4 years ago |
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dkhayes117
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d65aabb952
add cycle[h].rs, instret[h].rs, and mcounteren.rs modules
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4 years ago |
 bors[bot]
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39ff09eefe
Merge #53
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4 years ago |
 Nixon Enraght-Moony
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4bd6d68552
Update link (riscv to risc-v)
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4 years ago |
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bors[bot]
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6392fa9520
Merge #52
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5 years ago |
 luojia65
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7309236b6e
Use cargo fmt
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5 years ago |
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luojia65
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b144dd1709
Uppercase doc comments for `medeleg`
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5 years ago |
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luojia65
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db4a22c3c3
medeleg; small doc fix
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5 years ago |
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bors[bot]
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4d16f14ab3
Merge #51
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5 years ago |
 Vadim Kaushan
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f844c17c3a
Fix {S,U}tvec::trap_mode() functions to match Mtvec::trap_mode()
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5 years ago |
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bors[bot]
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3b8b0ad3c0
Merge #50
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5 years ago |
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Vadim Kaushan
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01148aab87
Fix CI
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5 years ago |
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Vadim Kaushan
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b395169b9a
Release v0.6.0
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5 years ago |
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Vadim Kaushan
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a614efc14b
Update copyright years
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5 years ago |
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Vadim Kaushan
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2daf0d2e76
Update MSRV to 1.42
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5 years ago |
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Vadim Kaushan
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4e6d9a0bf8
Add mising item to the change log
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5 years ago |
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bors[bot]
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ffb386ba46
Merge #48
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5 years ago |
 Karol Harasim
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6c91339f55
Remove vexriscv support.
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5 years ago |
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bors[bot]
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422a1625cf
Merge #47
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5 years ago |
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Vadim Kaushan
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66ebf47f28
Add change log entry
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5 years ago |
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Vadim Kaushan
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5211b5b699
Replace asm! with llvm_asm!
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5 years ago |
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bors[bot]
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d13776ad66
Merge #49
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5 years ago |
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Vadim Kaushan
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d9b7304666
Add change log entry
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5 years ago |
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Vadim Kaushan
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b0f75fb2e9
Update MSRV
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5 years ago |
