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Low level access to RISC-V processors

ИН на ревизия: 459421dbd3
Клонове Маркери
riscv
bors[bot] 459421dbd3 Merge #36 преди 5 години
.github 59d46795b2 A unified contributing experience. преди 6 години
bin b53e0a5cd2 add riscv32i target преди 5 години
ci 698cb306ea Enable gcc caching преди 6 години
src ea1f028a57 Add mideleg register support преди 5 години
.gitignore a51143d366 Implement asm functions преди 6 години
.travis.yml 7d4919a67c Add MSRV policy преди 6 години
CHANGELOG.md 7590a98318 Release v0.5.5 преди 5 години
CODE_OF_CONDUCT.md c1a3fe2dd9 Rename RISCV to RISC-V преди 6 години
Cargo.toml 459421dbd3 Merge #36 преди 5 години
README.md c1a3fe2dd9 Rename RISCV to RISC-V преди 6 години
asm.S a659a0cc39 Declare all the CSR registers in asm.S преди 5 години
asm.h a659a0cc39 Declare all the CSR registers in asm.S преди 5 години
assemble.sh b53e0a5cd2 add riscv32i target преди 5 години
build.rs a51143d366 Implement asm functions преди 6 години
check-blobs.sh a51143d366 Implement asm functions преди 6 години

README.md

crates.io crates.io Build Status

riscv

Low level access to RISC-V processors

This project is developed and maintained by the RISC-V team.

Documentation

License

Copyright 2019 RISC-V team

Permission to use, copy, modify, and/or distribute this software for any purpose with or without fee is hereby granted, provided that the above copyright notice and this permission notice appear in all copies.

THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.

Code of Conduct

Contribution to this crate is organized under the terms of the Rust Code of Conduct, the maintainer of this crate, the RISC-V team, promises to intervene to uphold that code of conduct.