 bors[bot]
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459421dbd3
Merge #36
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5 years ago |
 Vadim Kaushan
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7590a98318
Release v0.5.5
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5 years ago |
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Vadim Kaushan
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4bc23c6431
Add CHANGELOG.md
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5 years ago |
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bors[bot]
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e5e0888818
Merge #35
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5 years ago |
 Gui Andrade
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ea1f028a57
Add mideleg register support
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5 years ago |
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bors[bot]
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0259333c75
Merge #34
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5 years ago |
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Gui Andrade
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7a9aa062a0
Allow writing directly to satp register
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5 years ago |
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Gui Andrade
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95c52341c4
mip: Add set/clear functions for bits
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5 years ago |
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bors[bot]
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0eda3c511c
Merge #32
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5 years ago |
 Ales Katona
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73f45e3dbf
Merge branch 'master' into ustatus
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5 years ago |
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bors[bot]
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9d68612325
Merge #33
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5 years ago |
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Vadim Kaushan
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b834ae45a5
Do not use bare-metal v0.2.5 (changes MSRV)
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5 years ago |
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Ales Katona
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8840aee369
ucause only as readable bits
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5 years ago |
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Ales Katona
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e1232ed680
clean up formatting
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5 years ago |
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Ales Katona
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cdf6a33665
remove XS and FS from ustatus
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5 years ago |
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Ales Katona
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13831f7a80
revert scause specific trap/exceptions
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5 years ago |
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Ales Katona
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f443bcf698
remove invalid comment
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5 years ago |
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Ales Katona
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30555e4d79
fix typos in asm calls
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5 years ago |
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Ales Katona
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49446ad869
fix ustatus doc typos
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5 years ago |
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Ales Katona
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2180ef44d5
add user trap setup and handling registers
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5 years ago |
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bors[bot]
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4094a32f43
Merge #30
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5 years ago |
 Sebastien Bourdeauducq
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b53e0a5cd2
add riscv32i target
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5 years ago |
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bors[bot]
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7f1e4a56cf
Merge #31
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5 years ago |
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Vadim Kaushan
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d3dc245ce4
Bump version (0.5.4)
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5 years ago |
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Vadim Kaushan
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31f4127702
Add PMP CSRs
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5 years ago |
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Vadim Kaushan
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f37ab221c8
Implement hpmcounter*[h], mhpmcounter*[h], mhpmevent* CSRs
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5 years ago |
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Vadim Kaushan
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298a8b6f6e
Provide write() for mepc
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5 years ago |
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Vadim Kaushan
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7a8d3d1f6c
Implement mscratch and mtval registers
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5 years ago |
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Vadim Kaushan
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00367d4fd2
Add sections to the registers module
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5 years ago |
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Vadim Kaushan
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370a654d2c
Regenerate binaries
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5 years ago |
