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Low level access to RISC-V processors

Puu: 8baa254307
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riscv
Román Cárdenas 8baa254307 move all assembly to asm.rs 1 vuosi sitten
.github 8baa254307 move all assembly to asm.rs 1 vuosi sitten
riscv 3384fc8b19 Prepare for releases 1 vuosi sitten
riscv-pac 3384fc8b19 Prepare for releases 1 vuosi sitten
riscv-rt 8baa254307 move all assembly to asm.rs 1 vuosi sitten
riscv-semihosting 3384fc8b19 Prepare for releases 1 vuosi sitten
.gitignore 4344b03e88 Remove bit_field dependency 1 vuosi sitten
CODE_OF_CONDUCT.md 4bd6d68552 Update link (riscv to risc-v) 4 vuotta sitten
Cargo.toml e70afe47bd adjust the workspace 1 vuosi sitten
README.md e70afe47bd adjust the workspace 1 vuosi sitten

README.md

RISC-V crates

This repository contains various crates useful for writing Rust programs on RISC-V microcontrollers:

  • riscv: CPU registers access and intrinsics
  • riscv-pac: Common traits to be implemented by RISC-V PACs
  • riscv-rt: Startup code and interrupt handling
  • riscv-semihosting: Semihosting for RISC-V processors

This project is developed and maintained by the RISC-V team.

Contribution

Unless you explicitly state otherwise, any contribution intentionally submitted for inclusion in the work by you, as defined in the Apache-2.0 license, shall be dual licensed as above, without any additional terms or conditions.

Code of Conduct

Contribution to this crate is organized under the terms of the Rust Code of Conduct, the maintainer of this crate, the RISC-V team, promises to intervene to uphold that code of conduct.