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Low level access to RISC-V processors

Aborescence: 8baa254307
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riscv
Román Cárdenas 8baa254307 move all assembly to asm.rs il y a 1 an
.github 8baa254307 move all assembly to asm.rs il y a 1 an
riscv 3384fc8b19 Prepare for releases il y a 1 an
riscv-pac 3384fc8b19 Prepare for releases il y a 1 an
riscv-rt 8baa254307 move all assembly to asm.rs il y a 1 an
riscv-semihosting 3384fc8b19 Prepare for releases il y a 1 an
.gitignore 4344b03e88 Remove bit_field dependency il y a 1 an
CODE_OF_CONDUCT.md 4bd6d68552 Update link (riscv to risc-v) il y a 4 ans
Cargo.toml e70afe47bd adjust the workspace il y a 1 an
README.md e70afe47bd adjust the workspace il y a 1 an

README.md

RISC-V crates

This repository contains various crates useful for writing Rust programs on RISC-V microcontrollers:

  • riscv: CPU registers access and intrinsics
  • riscv-pac: Common traits to be implemented by RISC-V PACs
  • riscv-rt: Startup code and interrupt handling
  • riscv-semihosting: Semihosting for RISC-V processors

This project is developed and maintained by the RISC-V team.

Contribution

Unless you explicitly state otherwise, any contribution intentionally submitted for inclusion in the work by you, as defined in the Apache-2.0 license, shall be dual licensed as above, without any additional terms or conditions.

Code of Conduct

Contribution to this crate is organized under the terms of the Rust Code of Conduct, the maintainer of this crate, the RISC-V team, promises to intervene to uphold that code of conduct.