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Low level access to RISC-V processors

Koks: 99e189199b
Atzari Tagi
riscv
Vadim Kaushan 99e189199b Release v0.5.6 5 gadi atpakaļ
.github 59d46795b2 A unified contributing experience. 6 gadi atpakaļ
bin 8f7f5412e9 bin: rebuild asm file with vexriscv instructions 5 gadi atpakaļ
ci 698cb306ea Enable gcc caching 6 gadi atpakaļ
src 54a0364304 register: add vexriscv-specific registers 5 gadi atpakaļ
.gitignore a51143d366 Implement asm functions 6 gadi atpakaļ
.travis.yml 7d4919a67c Add MSRV policy 6 gadi atpakaļ
CHANGELOG.md 99e189199b Release v0.5.6 5 gadi atpakaļ
CODE_OF_CONDUCT.md c1a3fe2dd9 Rename RISCV to RISC-V 6 gadi atpakaļ
Cargo.toml 99e189199b Release v0.5.6 5 gadi atpakaļ
README.md c1a3fe2dd9 Rename RISCV to RISC-V 6 gadi atpakaļ
asm.S 54a0364304 register: add vexriscv-specific registers 5 gadi atpakaļ
asm.h a659a0cc39 Declare all the CSR registers in asm.S 5 gadi atpakaļ
assemble.ps1 f54f90f31c assemble: add powershell script 5 gadi atpakaļ
assemble.sh b53e0a5cd2 add riscv32i target 5 gadi atpakaļ
build.rs a51143d366 Implement asm functions 6 gadi atpakaļ
check-blobs.sh a51143d366 Implement asm functions 6 gadi atpakaļ

README.md

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riscv

Low level access to RISC-V processors

This project is developed and maintained by the RISC-V team.

Documentation

License

Copyright 2019 RISC-V team

Permission to use, copy, modify, and/or distribute this software for any purpose with or without fee is hereby granted, provided that the above copyright notice and this permission notice appear in all copies.

THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.

Code of Conduct

Contribution to this crate is organized under the terms of the Rust Code of Conduct, the maintainer of this crate, the RISC-V team, promises to intervene to uphold that code of conduct.