Startsida Utforska Hjälp
Logga in
DragonOS-Community
/
riscv
spegling av https://github.com/DragonOS-Community/riscv
4
0
Fork 0
Filer Ärenden 0 Wiki

Low level access to RISC-V processors

Träd: bb5ce6700d
Grenar Taggar
riscv
Jeremy Fitzhardinge bb5ce6700d Updated CHANGELOG 1 år sedan
.github 4dc63f6743 minor changes 1 år sedan
riscv bb5ce6700d Updated CHANGELOG 1 år sedan
riscv-pac 3384fc8b19 Prepare for releases 1 år sedan
riscv-rt fafec2e5ef Publish latest riscv-rt patch on crates.io 1 år sedan
riscv-semihosting 3384fc8b19 Prepare for releases 1 år sedan
.gitignore 4344b03e88 Remove bit_field dependency 1 år sedan
CODE_OF_CONDUCT.md 4bd6d68552 Update link (riscv to risc-v) 4 år sedan
Cargo.toml e70afe47bd adjust the workspace 1 år sedan
README.md e70afe47bd adjust the workspace 1 år sedan

README.md

RISC-V crates

This repository contains various crates useful for writing Rust programs on RISC-V microcontrollers:

  • riscv: CPU registers access and intrinsics
  • riscv-pac: Common traits to be implemented by RISC-V PACs
  • riscv-rt: Startup code and interrupt handling
  • riscv-semihosting: Semihosting for RISC-V processors

This project is developed and maintained by the RISC-V team.

Contribution

Unless you explicitly state otherwise, any contribution intentionally submitted for inclusion in the work by you, as defined in the Apache-2.0 license, shall be dual licensed as above, without any additional terms or conditions.

Code of Conduct

Contribution to this crate is organized under the terms of the Rust Code of Conduct, the maintainer of this crate, the RISC-V team, promises to intervene to uphold that code of conduct.