 Vadim Kaushan
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99e189199b
Release v0.5.6
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%!s(int64=5) %!d(string=hai) anos |
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Vadim Kaushan
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9a65a7023e
Update CHANGELOG.md
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%!s(int64=5) %!d(string=hai) anos |
 bors[bot]
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30af64cad7
Merge #37
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 Sean Cross
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f54f90f31c
assemble: add powershell script
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Sean Cross
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8f7f5412e9
bin: rebuild asm file with vexriscv instructions
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Sean Cross
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54a0364304
register: add vexriscv-specific registers
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%!s(int64=5) %!d(string=hai) anos |
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bors[bot]
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459421dbd3
Merge #36
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Vadim Kaushan
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7590a98318
Release v0.5.5
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%!s(int64=5) %!d(string=hai) anos |
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Vadim Kaushan
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4bc23c6431
Add CHANGELOG.md
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bors[bot]
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e5e0888818
Merge #35
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 Gui Andrade
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ea1f028a57
Add mideleg register support
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bors[bot]
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0259333c75
Merge #34
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Gui Andrade
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7a9aa062a0
Allow writing directly to satp register
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Gui Andrade
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95c52341c4
mip: Add set/clear functions for bits
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bors[bot]
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0eda3c511c
Merge #32
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 Ales Katona
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73f45e3dbf
Merge branch 'master' into ustatus
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bors[bot]
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9d68612325
Merge #33
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Vadim Kaushan
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b834ae45a5
Do not use bare-metal v0.2.5 (changes MSRV)
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Ales Katona
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8840aee369
ucause only as readable bits
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Ales Katona
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e1232ed680
clean up formatting
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Ales Katona
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cdf6a33665
remove XS and FS from ustatus
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Ales Katona
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13831f7a80
revert scause specific trap/exceptions
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Ales Katona
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f443bcf698
remove invalid comment
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Ales Katona
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30555e4d79
fix typos in asm calls
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Ales Katona
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49446ad869
fix ustatus doc typos
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Ales Katona
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2180ef44d5
add user trap setup and handling registers
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bors[bot]
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4094a32f43
Merge #30
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 Sebastien Bourdeauducq
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b53e0a5cd2
add riscv32i target
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bors[bot]
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7f1e4a56cf
Merge #31
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Vadim Kaushan
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d3dc245ce4
Bump version (0.5.4)
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