Low level access to RISC-V processors

Vadim Kaushan a614efc14b Update copyright years преди 4 години
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.gitignore a51143d366 Implement asm functions преди 6 години
.travis.yml 2daf0d2e76 Update MSRV to 1.42 преди 4 години
CHANGELOG.md 2daf0d2e76 Update MSRV to 1.42 преди 4 години
CODE_OF_CONDUCT.md c1a3fe2dd9 Rename RISCV to RISC-V преди 6 години
Cargo.toml 3aaa2f48eb Update dependencies преди 4 години
README.md a614efc14b Update copyright years преди 4 години
asm.S 6c91339f55 Remove vexriscv support. преди 4 години
asm.h a659a0cc39 Declare all the CSR registers in asm.S преди 5 години
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README.md

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riscv

Low level access to RISC-V processors

This project is developed and maintained by the RISC-V team.

Documentation

Minimum Supported Rust Version (MSRV)

This crate is guaranteed to compile on stable Rust 1.42.0 and up. It might compile with older versions but that may change in any new patch release.

License

Copyright 2019-2020 RISC-V team

Permission to use, copy, modify, and/or distribute this software for any purpose with or without fee is hereby granted, provided that the above copyright notice and this permission notice appear in all copies.

THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.

Code of Conduct

Contribution to this crate is organized under the terms of the Rust Code of Conduct, the maintainer of this crate, the RISC-V team, promises to intervene to uphold that code of conduct.