 Vadim Kaushan
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a804abda7e
Remove #![deny(warnings)] (anti-pattern)
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 bors[bot]
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c58e34961d
Merge #43
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 Ales Katona
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184d511b1c
fix cargo fmt
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bors[bot]
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16644b6cad
Merge #40
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bors[bot]
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400fe44fa9
Merge #42
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bors[bot]
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bad98ec38d
Merge #41
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 Ilya Epifanov
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040eb2c805
using `riscv-target` with compatible MSRV
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Ilya Epifanov
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0b1131dd20
Only checking for necessary extensions when linking
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Vadim Kaushan
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b7319d00d8
Allow nightly build to fail
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Vadim Kaushan
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7ecbf66955
Remove obsolete CI hack
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 Diego Barrios Romero
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2b5315e834
Document MSRV on README
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bors[bot]
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255ef60f1a
Merge #38
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Vadim Kaushan
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99e189199b
Release v0.5.6
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Vadim Kaushan
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9a65a7023e
Update CHANGELOG.md
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bors[bot]
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30af64cad7
Merge #37
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 Sean Cross
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f54f90f31c
assemble: add powershell script
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Sean Cross
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8f7f5412e9
bin: rebuild asm file with vexriscv instructions
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Sean Cross
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54a0364304
register: add vexriscv-specific registers
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bors[bot]
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459421dbd3
Merge #36
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Vadim Kaushan
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7590a98318
Release v0.5.5
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Vadim Kaushan
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4bc23c6431
Add CHANGELOG.md
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bors[bot]
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e5e0888818
Merge #35
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 Gui Andrade
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ea1f028a57
Add mideleg register support
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bors[bot]
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0259333c75
Merge #34
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Gui Andrade
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7a9aa062a0
Allow writing directly to satp register
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Gui Andrade
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95c52341c4
mip: Add set/clear functions for bits
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bors[bot]
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0eda3c511c
Merge #32
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 Ales Katona
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73f45e3dbf
Merge branch 'master' into ustatus
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bors[bot]
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9d68612325
Merge #33
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Vadim Kaushan
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b834ae45a5
Do not use bare-metal v0.2.5 (changes MSRV)
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